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| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 11:02:28 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:39:29 +0100 |
| commit | a97330e723cf3c639a951329ac5fe2797528249b (patch) | |
| tree | 9085698ab114327b7807d6763fead55c0f4b8d6e /include | |
| parent | ff6054520cc86ac2f34c21bcc2e44ede50b56cdc (diff) | |
| download | gdb-a97330e723cf3c639a951329ac5fe2797528249b.zip gdb-a97330e723cf3c639a951329ac5fe2797528249b.tar.gz gdb-a97330e723cf3c639a951329ac5fe2797528249b.tar.bz2 | |
[PATCH, BINUTILS, AARCH64, 8/9] Add SCXTNUM_ELx and ID_PFR2_EL1 system registers
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/exploration-tools)
The encodings can be found in the System Register XML.
This patch adds the new system registers SCXTNUM_ELx and ID_PFR2_EL1.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New.
(AARCH64_FEATURE_ID_PFR2): New.
(AARCH64_ARCH_V8_5): Add both by default.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
(aarch64_sys_reg_supported_p): New checks for above.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* testsuite/gas/aarch64/sysreg-4.s: Test registers
scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
* testsuite/gas/aarch64/sysreg-4.d: Likewise.
* testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 9 |
2 files changed, 14 insertions, 1 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index f57d205..ed5dcf2 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,11 @@ 2018-10-09 Sudakshina Das <sudi.das@arm.com> + * opcode/aarch64.h (AARCH64_FEATURE_SCXTNUM): New. + (AARCH64_FEATURE_ID_PFR2): New. + (AARCH64_ARCH_V8_5): Add both by default. + +2018-10-09 Sudakshina Das <sudi.das@arm.com> + * opcode/aarch64.h (AARCH64_FEATURE_BTI): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default. (aarch64_opnd): Add AARCH64_OPND_BTI_TARGET. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 144ec7e..b56f907 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -78,6 +78,11 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_RNG 0x80000000000ULL /* BTI instructions. */ #define AARCH64_FEATURE_BTI 0x100000000000ULL +/* SCXTNUM_ELx. */ +#define AARCH64_FEATURE_SCXTNUM 0x200000000000ULL +/* ID_PFR2 instructions. */ +#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL + /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ @@ -108,7 +113,9 @@ typedef uint32_t aarch64_insn; | AARCH64_FEATURE_SB \ | AARCH64_FEATURE_PREDRES \ | AARCH64_FEATURE_CVADP \ - | AARCH64_FEATURE_BTI) + | AARCH64_FEATURE_BTI \ + | AARCH64_FEATURE_SCXTNUM \ + | AARCH64_FEATURE_ID_PFR2) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) |