AArch64: Add SVE constraints verifier.

This patch adds the verification rules for move prefix constraints.

The Arm SVE instruction MOVPRFX introduces[1] constraints on the instruction at
PC+4. Particularly the following constraints are handled by this patch

* MOVPRFX must be followed by an instruction.
* MOVPRFX can only be followed by non-layout altering directives.
* MOVPRFX destination register MUST be used as the destination register in the
  instruction at PC+4, and is not allowed to be used in any other position other than
  destructive input.  This includes registers that architecturally overlap. e.g. x1
  should be treated as z1.
* MOVPRFX must be followed by a restricted set of SVE instructions.
* The size of the destination register of MOVPRFX must be equal to that of
  the operation at PC+4.
* The predicate register and operation of MOVPRFX must match that of the instruction
  at PC+4
* The predicated instruction at PC+4 must use the merging predicate.
* Architectural aliases and pseudo-instructions need to be supported as well.
* MOVPRFX cannot be the last instruction in a sequence

Any failure to adhere to any of these constrains will emit an assembly warning
and a disassembly note.

[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a

include/

	* opcode/aarch64.h (aarch64_inst): Remove.
	(enum err_type): Add ERR_VFI.
	(aarch64_is_destructive_by_operands): New.
	(init_insn_sequence): New.
	(aarch64_decode_insn): Remove param name.

opcodes/

	* aarch64-opc.c (init_insn_block): New.
	(verify_constraints, aarch64_is_destructive_by_operands): New.
	* aarch64-opc.h (verify_constraints): New.

gas/

        * config/tc-aarch64.c (output_operand_error_report): Order warnings.

2 files changed, 16 insertions, 2 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index dc200a1..a909db3 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,5 +1,13 @@
 2018-10-03  Tamar Christina  <tamar.christina@arm.com>
 
+	* opcode/aarch64.h (aarch64_inst): Remove.
+	(enum err_type): Add ERR_VFI.
+	(aarch64_is_destructive_by_operands): New.
+	(init_insn_sequence): New.
+	(aarch64_decode_insn): Remove param name.
+
+2018-10-03  Tamar Christina  <tamar.christina@arm.com>
+
 	* opcode/aarch64.h (struct aarch64_opcode): Expand verifiers to take
 	more arguments.
 
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 751d7bb..f66ee86 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -648,6 +648,7 @@ enum err_type
   ERR_UND,
   ERR_UNP,
   ERR_NYI,
+  ERR_VFI,
   ERR_NR_ENTRIES
 };
 
@@ -1065,7 +1066,6 @@ struct aarch64_inst
   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 };
 
-typedef struct aarch64_inst aarch64_inst;
 
 /* Diagnosis related declaration and interface.  */
 
@@ -1190,6 +1190,9 @@ extern aarch64_opnd_qualifier_t
 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 				const aarch64_opnd_qualifier_t, int);
 
+extern bfd_boolean
+aarch64_is_destructive_by_operands (const aarch64_opcode *);
+
 extern int
 aarch64_num_of_operands (const aarch64_opcode *);
 
@@ -1201,7 +1204,10 @@ aarch64_zero_register_p (const aarch64_opnd_info *);
 
 extern enum err_type
 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
-		     aarch64_operand_error *errors);
+		     aarch64_operand_error *);
+
+extern void
+init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
 
 /* Given an operand qualifier, return the expected data element size
    of a qualified operand.  */