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| author | Palmer Dabbelt <palmer@sifive.com> | 2018-10-02 08:26:32 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2018-10-02 08:26:32 -0700 |
| commit | 64a336ac134ebd7f9452a7088e90e29551465251 (patch) | |
| tree | 43af5101dd733eaef5710e6ead74105397cc20ee /include | |
| parent | c1168a2f66553cd4730931cf59e3be8378a1a03f (diff) | |
| download | gdb-64a336ac134ebd7f9452a7088e90e29551465251.zip gdb-64a336ac134ebd7f9452a7088e90e29551465251.tar.gz gdb-64a336ac134ebd7f9452a7088e90e29551465251.tar.bz2 | |
RISC-V: Add fence.tso instruction
The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso". This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.
I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets. I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.
gas/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* testsuite/gas/riscv/fence-tso.d: New file.
* testsuite/gas/riscv/fence-tso.s: Likewise.
include/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
(MASK_FENCE_TSO): Likewise.
opcodes/ChangeLog
2018-10-02 Palmer Dabbelt <palmer@sifive.com>
* riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 2 |
2 files changed, 7 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index d0e0d72..98d4241 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2018-10-02 Palmer Dabbelt <palmer@sifive.com> + + * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define. + (MASK_FENCE_TSO): Likewise. + 2018-10-01 Cupertino Miranda <cmiranda@synopsys.com> * arc-reloc.def (ARC_TLS_LE_32): Updated reloc formula. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 60bd2f9..f09200c 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -141,6 +141,8 @@ #define MASK_FENCE 0x707f #define MATCH_FENCE_I 0x100f #define MASK_FENCE_I 0x707f +#define MATCH_FENCE_TSO 0x8330000f +#define MASK_FENCE_TSO 0xfff0707f #define MATCH_MUL 0x2000033 #define MASK_MUL 0xfe00707f #define MATCH_MULH 0x2001033 |