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2023-06-15Add MIPS Allegrex CPU as a MIPS2-based CPUDavid Guillen Fandos2-0/+7
The Allegrex CPU was created by Sony Interactive Entertainment to power their portable console, the PlayStation Portable. The pspdev organization maintains all sorts of tools to create software for said device including documentation. Signed-off-by: David Guillen Fandos <david@davidgf.net>
2023-06-15Revert "MIPS: add MT ASE support for micromips32"Maciej W. Rozycki1-25/+10
This reverts commit acce83dacff0ce43677410c67aaae32817afe991. It was applied unapproved.
2023-06-15Revert "MIPS: sync oprand char usage between mips and micromips"Maciej W. Rozycki1-12/+2
This reverts commit 5b207b919483f67311a73dfc1de8897ecfd8e776. It was applied unapproved.
2023-06-09ecoff find_nearest_line and final link leaksAlan Modra1-1/+4
Freeing ecoff_debug_info "pointers to the unswapped symbolic info" isn't a simple matter, due to differing allocation strategies. In _bfd_ecoff_slurp_symbolic_info the pointers are to objalloc memory. In the ecoff linker they are to separately malloc'd memory. In gas we have most (obj-elf) or all (obj-ecoff) into a single malloc'd buffer. This patch fixes the leaks for binutils and ld, leaving the gas leaks for another day. The mips elf backend already had this covered, and the ecoff backend had a pointer, raw_syments used as a flag, so most of the patch is moving these around a little so they are accessible for both ecoff and elf. include/ * coff/ecoff.h (struct ecoff_debug_info): Add alloc_syments. bfd/ * libecoff.h (struct ecoff_tdata): Delete raw_syments. * elfxx-mips.c (free_ecoff_debug): Delete. Replace uses with _bfd_ecoff_free_ecoff_debug_info. (_bfd_mips_elf_final_link): Init debug.alloc_syments. * ecofflink.c (_bfd_ecoff_free_ecoff_debug_info): New function. * ecoff.c (_bfd_ecoff_bfd_free_cached_info): Call _bfd_ecoff_free_ecoff_debug_info. (_bfd_ecoff_slurp_symbolic_info): Replace uses of raw_syments with alloc_syments. (ecoff_final_link_debug_accumulate): Likewise. Use _bfd_ecoff_free_ecoff_debug_info. (_bfd_ecoff_bfd_copy_private_bfd_data): Set alloc_syments for copied output. * elf64-alpha.c (elf64_alpha_read_ecoff_info): Use _bfd_ecoff_free_ecoff_debug_info. * libbfd-in.h (_bfd_ecoff_free_ecoff_debug_info): Declare. * libbfd.h: Regenerate. gas/ * config/obj-ecoff.c (ecoff_frob_file): Set alloc_syments. * config/obj-elf.c (elf_frob_file_after_relocs): Likewise.
2023-06-06libsframe: fix cosmetic issues and typosIndu Bhagat1-1/+1
include/ * sframe-api.h (sframe_decoder_get_num_fidx): Use extern. libsframe/ * sframe-dump.c (dump_sframe_func_with_fres): Fix line length. * sframe.c (sframe_frame_row_entry_copy): Likewise. (sframe_decode_fre_start_address): Use the intended type uint32_t.
2023-06-05MIPS: sync oprand char usage between mips and micromipsYunQiang Su1-2/+12
We should try our best to make mips32 using the same oprand char with micromips. So for mips32, we use: ^ is added for 5bit sa oprand for some new DSPr2 instructions: APPEND, PREPEND, PRECR_SRA[_R].PH.W the LSB bit is 11, like RD. +t is removed for coprocessor 0 destination register. 'E' does the samething. +t is now used for RX oprand for MFTR/MTTR (MT ASE) ? is added for sel oprand for MFTR/MTTR (MT ASE) For mips32, the position of sel in MFTR/MTTR is same with mfc0 etc, while for micromips, they are different. We also add an extesion format of cftc2/cttc2/mftc2/mfthc2/mttc2/mtthc2: concatenating rs with rx as the index of control or data.
2023-06-05MIPS: add MT ASE support for micromips32YunQiang Su1-10/+25
These instructions are descripted in MD00768. MIPS® Architecture for Programmers Volume IV-f: The MIPS® MT Module for the microMIPS32™ Architecture Document Number: MD00768 Revision 1.12 July 16, 2013 https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00768-1C-microMIPS32MT-AFP-01.12.pdf
2023-06-01libsframe: avoid using magic numberIndu Bhagat1-1/+4
Define a new constant for the maximum number of stack offsets handled in libsframe, and use it. Note that the SFrame format does not define such a constant (limit). This is an implmentation-defined constant in libsframe. include/ * sframe-api.h (MAX_NUM_STACK_OFFSETS): New definition. libsframe/ * sframe.c (sframe_fre_sanity_check_p): Use it.
2023-06-01RISC-V: PR30449, Add lga assembler macro support.Jim Wilson1-0/+1
Originally discussion, https://github.com/riscv/riscv-isa-manual/pull/539 Added new load address pseudo instruction which is always expanded to GOT access, no matter the .option rvc is set or not. gas/ PR 30449 * config/tc-riscv.c (macro): Add M_LGA support. * testsuite/gas/riscv/la-variants.d: New. * testsuite/gas/riscv/la-variants.s: New. include/ PR 30449 * opcode/riscv.h (M_LGA): New. opcodes/ PR 30449 * riscv-opc.c (riscv_opcodes): Add lga support.
2023-05-30LoongArch: include: Add support for linker relaxation.mengqinggang2-0/+23
Add relocs and gas LARCH_opts.relax option. include/ChangeLog: * elf/loongarch.h: Add relocs. * opcode/loongarch.h: Add LARCH_opts.relax and macro LARCH_NOP.
2023-05-30Define IMAGE_FILE_MACHINE_ARMNTAlan Modra1-0/+1
Same value as ARMV7PEMAGIC. https://learn.microsoft.com/en-us/windows/win32/sysinfo/image-file-machine-constants * coff/pe.h (IMAGE_FILE_MACHINE_ARMNT): Define.
2023-05-30Delete include/aout/encap.hAlan Modra1-135/+0
This file is unused and as the header comment says, obsolete.
2023-05-26Remove duplicate definitionAndreas Schwab2-2/+6
* coff/pe.h (IMAGE_FILE_MACHINE_AMD64): Remove duplicate definition. Alphabetize.
2023-05-22Re: readelf: Support SHT_RELR/DT_RELR for -rAlan Modra1-1/+4
Revert value of DT_ENCODING to as it was before commit a7fd118627, and adjust readelf. include/ * elf/common.h (DT_ENCODING): Set back to 32. binutils/ * readelf.c (struct filedata): Don't size dynamic_info array using DT_ENCODING.
2023-05-19RISC-V: Support subtraction of .uleb128.Kuan-Lin Chen1-0/+3
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/commit/96d6e190e9fc04a8517f9ff7fb9aed3e9876cbd6 There are some known limitations for now, * Do not shrink the length of the uleb128 value, even if the value is reduced after relaxations. Also reports error if the length grows up. * The R_RISCV_SET_ULEB128 needs to be paired with and be placed before the R_RISCV_SUB_ULEB128. bfd/ * bfd-in2.h: Regenerated. * elfnn-riscv.c (perform_relocation): Perform R_RISCV_SUB_ULEB128 and R_RISCV_SET_ULEB128 relocations. Do not shrink the length of the uleb128 value, and report error if the length grows up. Called the generic functions, _bfd_read_unsigned_leb128 and _bfd_write_unsigned_leb128, to encode the uleb128 into the section contents. (riscv_elf_relocate_section): Make sure that the R_RISCV_SET_ULEB128 must be paired with and be placed before the R_RISCV_SUB_ULEB128. * elfxx-riscv.c (howto_table): Added R_RISCV_SUB_ULEB128 and R_RISCV_SET_ULEB128. (riscv_reloc_map): Likewise. (riscv_elf_ignore_reloc): New function. * libbfd.h: Regenerated. * reloc.c (BFD_RELOC_RISCV_SET_ULEB128, BFD_RELOC_RISCV_SUB_ULEB128): New relocations to support .uleb128 subtraction. gas/ * config/tc-riscv.c (md_apply_fix): Added BFD_RELOC_RISCV_SET_ULEB128 and BFD_RELOC_RISCV_SUB_ULEB128. (s_riscv_leb128): Updated to allow uleb128 subtraction. (riscv_insert_uleb128_fixes): New function, scan uleb128 subtraction expressions and insert fixups for them. (riscv_md_finish): Called riscv_insert_uleb128_fixes for all sections. include/ * elf/riscv.h ((R_RISCV_SET_ULEB128, (R_RISCV_SUB_ULEB128): Defined. ld/ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated. * testsuite/ld-riscv-elf/uleb128*: New testcase for uleb128 subtraction. binutils/ * testsuite/binutils-all/nm.exp: Updated since RISCV supports .uleb128.
2023-05-17PR29961, plugin-api.h: "Could not detect architecture endianess"Alan Modra1-22/+23
Found when attempting to build binutils on sparc sunos-5.8 where sys/byteorder.h defines _BIG_ENDIAN but not any of the BYTE_ORDER variants. This patch adds the extra tests to cope with the old machine, and tidies the header a little. PR 29961 plugin-api.h: When handling non-gcc or gcc < 4.6.0 include necessary header files before testing macros. Make more use of #elif. Test _LITTLE_ENDIAN and _BIG_ENDIAN in final tests.
2023-05-17gcc-4.5 build fixesAlan Modra1-2/+0
Trying to build binutils with an older gcc currently fails. Working around these gcc bugs is not onerous so let's fix them. bfd/ * elf32-csky.c (csky_elf_size_dynamic_sections): Don't type-pun pointer. * elf32-rl78.c (rl78_compute_complex_reloc): Rename "stat" variable to "status". gas/ * compress-debug.c (compress_finish): Supply all fields in ZSTD_inBuffer initialisation. include/ * xtensa-dynconfig.h (xtensa_isa_internal): Delete unnecessary forward declaration. opcodes/ * loongarch-opc.c: Supply all fields of zero struct initialisation in various opcode tables.
2023-05-11Add LDPT_REGISTER_CLAIM_FILE_HOOK_V2 linker plugin hook [GCC PR109128]Joseph Myers1-0/+16
This is one part of the fix for GCC PR109128, along with a corresponding GCC change. Without this patch, what happens in the linker, when an unused object in a .a file has offload data, is that elf_link_is_defined_archive_symbol calls bfd_link_plugin_object_p, which ends up calling the plugin's claim_file_handler, which then records the object as one with offload data. That is, the linker never decides to use the object in the first place, but use of this _p interface (called as part of trying to decide whether to use the object) results in the plugin deciding to use its offload data (and a consequent mismatch in the offload data present at runtime). The new hook allows the linker plugin to distinguish calls to claim_file_handler that know the object is being used by the linker (from ldmain.c:add_archive_element), from calls that don't know it's being used by the linker (from elf_link_is_defined_archive_symbol); in the latter case, the plugin should avoid recording the object as one with offload data. bfd/ * plugin.c (struct plugin_list_entry): Add claim_file_v2. (register_claim_file_v2): New. (try_load_plugin): Use LDPT_REGISTER_CLAIM_FILE_HOOK_V2. (ld_plugin_object_p): Take second argument. (bfd_link_plugin_object_p): Update call to ld_plugin_object_p. (register_ld_plugin_object_p): Update argument prototype. (bfd_plugin_object_p): Update call to ld_plugin_object_p. * plugin.h (register_ld_plugin_object_p): Update argument prototype. include/ * plugin.api.h (ld_plugin_claim_file_handler_v2) (ld_plugin_register_claim_file_v2) (LDPT_REGISTER_CLAIM_FILE_HOOK_V2): New. (struct ld_plugin_tv): Add tv_register_claim_file_v2. ld/ * plugin.c (struct plugin): Add claim_file_handler_v2. (LDPT_REGISTER_CLAIM_FILE_HOOK_V2): New. (plugin_object_p): Add second argument. Update call to plugin_call_claim_file. (register_claim_file_v2): New. (set_tv_header): Handle LDPT_REGISTER_CLAIM_FILE_HOOK_V2. (plugin_call_claim_file): Add argument known_used. (plugin_maybe_claim): Update call to plugin_object_p. * testplug.c, testplug2.c, testplug3.c, testplug4.c: Handle LDPT_REGISTER_CLAIM_FILE_HOOK_V2. * testsuite/ld-plugin/plugin-1.d, testsuite/ld-plugin/plugin-10.d, testsuite/ld-plugin/plugin-11.d, testsuite/ld-plugin/plugin-13.d, testsuite/ld-plugin/plugin-14.d, testsuite/ld-plugin/plugin-15.d, testsuite/ld-plugin/plugin-16.d, testsuite/ld-plugin/plugin-17.d, testsuite/ld-plugin/plugin-18.d, testsuite/ld-plugin/plugin-19.d, testsuite/ld-plugin/plugin-2.d, testsuite/ld-plugin/plugin-26.d, testsuite/ld-plugin/plugin-3.d, testsuite/ld-plugin/plugin-30.d, testsuite/ld-plugin/plugin-4.d, testsuite/ld-plugin/plugin-5.d, testsuite/ld-plugin/plugin-6.d, testsuite/ld-plugin/plugin-7.d, testsuite/ld-plugin/plugin-8.d, testsuite/ld-plugin/plugin-9.d: Update test expectations.
2023-04-28Re: Keeping track of rs6000-coff archive element pointersAlan Modra1-5/+5
Commit de7b90610e9e left a hole in the element checking, explained by the comment added to _bfd_xcoff_openr_next_archived_file. While fixing this, tidy some types used to hold unsigned values so that casts are not needed to avoid signed/unsigned comparison warnings. Also tidy a few things in xcoff.h. bfd/ * coff-rs6000.c (_bfd_xcoff_openr_next_archived_file): Check that we aren't pointing back at the last element. Make filestart a ufile_ptr. Update for xcoff_artdata change. (_bfd_strntol, _bfd_strntoll): Return unsigned values. (_bfd_xcoff_slurp_armap): Make off a ufile_ptr. (add_ranges): Update for xcoff_artdata change. * libbfd-in.h (struct artdata): Make first_file_filepos a ufile_ptr. * libbfd.h: Regenerate. include/ * coff/xcoff.h (struct xcoff_artdata): Replace min_elt with ar_hdr_size. (xcoff_big_format_p): In the !SMALL_ARCHIVE case return true for anything but a small archive.
2023-04-26 RISC-V: Support XVentanaCondOps extensionPhilipp Tomsich2-0/+9
Ventana Micro has published the specification for their XVentanaCondOps ("conditional ops") extension at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf which contains two new instructions - vt.maskc - vt.maskcn that can be used in constructing branchless sequences for various conditional-arithmetic, conditional-logical, and conditional-select operations. To support such vendor-defined instructions in the mainline binutils, this change also adds a riscv_supported_vendor_x_ext secondary dispatch table (but also keeps the behaviour of allowing any unknow X-extension to be specified in addition to the known ones from this table). As discussed, this change already includes the planned/agreed future requirements for X-extensions (which are likely to be captured in the riscv-toolchain-conventions repository): - a public specification document is available (see above) and is referenced from the gas-documentation - the naming follows chapter 27 of the RISC-V ISA specification - instructions are prefixed by a vendor-prefix (vt for Ventana) to ensure that they neither conflict with future standard extensions nor clash with other vendors bfd/ChangeLog: * elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext. (riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS. gas/ChangeLog: * doc/c-riscv.texi: Add section to list custom extensions and their documentation URLs. * testsuite/gas/riscv/x-ventana-condops.d: New test. * testsuite/gas/riscv/x-ventana-condops.s: New test. include/ChangeLog: * opcode/riscv-opc.h Add vt.maskc and vt.maskcn. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS. opcodes/ChangeLog: * riscv-opc.c: Add vt.maskc and vt.maskcn. Series-version: 1 Series-to: binutils@sourceware.org Series-cc: Kito Cheng <kito.cheng@sifive.com> Series-cc: Nelson Chu <nelson.chu@sifive.com> Series-cc: Greg Favor <gfavor@ventanamicro.com> Series-cc: Christoph Muellner <cmuellner@gcc.gnu.org>
2023-04-21Keeping track of rs6000-coff archive element pointersAlan Modra1-22/+34
rs6000-coff archives use a linked list of file offsets, where each element points to the next element. The idea is to allow updating of large archives quickly without rewriting the whole archive. (binutils ar does not do this.) Unfortunately this is an easy target for fuzzers to create an archive that will cause ar or any other tool processing archives to hang. I'd implemented guards against pointing back to the previous element, but of course that didn't last long. So this patch implements a scheme to keep track of file offset ranges used by elements as _bfd_read_ar_hdr is called for each element. See the add_range function comment. I needed a place to stash the list, so chose the obvious artdata.tdata backend extension to archive's tdata, already used by xcoff. That involved a little cleanup, because while it would be possible to continue using different artdata.tdata for the big and small archives, it's nicer to use a union. If anyone is concerned this list of element ranges might grow large and thus significantly slow down the tools, adjacent ranges are merged. In fact something like "ar t" will only ever have one range on xcoff archives generated by binutils/ar. I agree there might still be a problem with ld random element access via the armap. include/ * coff/xcoff.h (SIZEOF_AR_FILE_HDR): Use sizeof. (SIZEOF_AR_FILE_HDR_BIG, SIZEOF_AR_HDR, SIZEOF_AR_HDR_BIG): Likewise. (struct ar_ranges, struct xcoff_artdata): New. (x_artdata): Define. (xcoff_big_format_p): Rewrite. (xcoff_ardata, xcoff_ardata_big): Delete. bfd/ * coff-rs6000.c: Replace uses of xcoff_ardata and xcoff_ardata_big throughout file. (_bfd_xcoff_archive_p): Adjust artdata.tdata allocation. (add_range): New function. (_bfd_xcoff_read_ar_hdr): Use it here. Fix memory leak. (_bfd_xcoff_openr_next_archived_file): Remove old sanity checks. Set up range for header. (xcoff_write_archive_contents_old): Make the temporary artdata.tdata used here to pass info down to _bfd_compute_and_write_armap a struct xcoff_artdata. (xcoff_write_archive_contents_big): Likewise. * coff64-rs6000.c: Replace uses of xcoff_ardata and xcoff_ardata_big throughout file. (xcoff64_archive_p): Adjust artdata.tdata allocation.
2023-04-19sframe: correct some typosIndu Bhagat1-2/+2
include/ * sframe.h: Correct a typo. libsframe/ * sframe.c: Likewise.
2023-03-30aarch64: Remove stray reglist variableRichard Sandiford1-1/+1
Sorry for not catching this during testing. I was using a host compiler that predated the switch to -fno-common.
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford1-0/+2
This patch adds the RPRFM (range prefetch) instruction. It was introduced as part of SME2, but it belongs to the prefetch hint space and so doesn't require any specific ISA flags. The aarch64_rprfmop_array initialiser (deliberately) only fills in the leading non-null elements.
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford1-1/+2
This patch adds the SVE FDOT, SDOT and UDOT instructions, which are available when FEAT_SME2 is implemented. The patch also reorders the existing SVE_Zm3_22_INDEX to keep the operands numerically sorted.
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-0/+3
There are two instruction formats here: - SQRSHR, SQRSHRU and UQRSHR, which operate on lists of two or four registers. - SQRSHRN, SQRSHRUN and UQRSHRN, which operate on lists of four registers. These are the first SME2 instructions to have immediate operands. The patch makes sure that, when parsing SME2 instructions with immediate operands, the new predicate-as-counter registers are parsed as registers rather than as #-less immediates.
2023-03-30aarch64: Add the SME2 saturating conversion instructionsRichard Sandiford1-0/+1
There are two instruction formats here: - SQCVT, SQCVTU and UQCVT, which operate on lists of two or four registers. - SQCVTN, SQCVTUN and UQCVTN, which operate on lists of four registers.
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford1-0/+5
SMLALL, SMLSLL, UMLALL and UMLSLL have the same format. USMLALL and SUMLALL allow the same operand types as those instructions, except that SUMLALL does not have the multi-vector x multi-vector forms (which would be redundant with USMLALL).
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-0/+4
The {BF,F,S,U}MLAL and {BF,F,S,U}MLSL instructions share the same encoding. They are the first instance of a ZA (as opposed to ZA tile) operand having a range of offsets. As with ZA tiles, the expected range size is encoded in the operand-specific data field.
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford1-0/+2
2023-03-30aarch64: Add the SME2 maximum/minimum instructionsRichard Sandiford1-0/+1
This patch adds the SME2 multi-register forms of F{MAX,MIN}{,NM} and {S,U}{MAX,MIN}. SQDMULH, SRSHL and URSHL have the same form as SMAX etc., so the patch adds them too.
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-0/+3
Add support for the SME2 ADD. SUB, FADD and FSUB instructions. SUB and FSUB have the same form as ADD and FADD, except that ADD also has a 2-operand accumulating form. The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the 64-bit FADD/FSUB instructions require FEAT_SME_F64F64. These are the first instructions to have tied register list operands, as opposed to tied single registers. The parse_operands change prevents unsuffixed Z registers (width==-1) from being treated as though they had an Advanced SIMD-style suffix (.4s etc.). It means that: Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}' becomes: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-0/+11
SME2 adds lookup table instructions for quantisation. They use a new lookup table register called ZT0. LUTI2 takes an unsuffixed SVE vector index of the form Zn[<imm>], which is the first time that this syntax has been used.
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-0/+11
Implementation-wise, the main things to note here are: - the WHILE* instructions have forms that return a pair of predicate registers. This is the first time that we've had lists of predicate registers, and they wrap around after register 15 rather than after register 31. - the predicate-as-counter WHILE* instructions have a fourth operand that specifies the vector length. We can treat this as an enumeration, except that immediate values aren't allowed. - PEXT takes an unsuffixed predicate index of the form PN<n>[<imm>]. This is the first instance of a vector/predicate index having no suffix.
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-0/+3
SME2 adds LD1 and ST1 variants for lists of 2 and 4 registers. The registers can be consecutive or strided. In the strided case, 2-register lists have a stride of 8, starting at register x0xxx. 4-register lists have a stride of 4, starting at register x00xx. The instructions are predicated on a predicate-as-counter register in the range pn8-pn15. Although we already had register fields with upper bounds of 7 and 15, this is the first plain register operand to have a nonzero lower bound. The patch uses the operand-specific data field to record the minimum value, rather than having separate inserters and extractors for each lower bound. This in turn required adding an extra bit to the field.
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-0/+10
SME2 defines new MOVA instructions for moving multiple registers to and from ZA. As with SME, the instructions are also available through MOV aliases. One notable feature of these instructions (and many other SME2 instructions) is that some register lists must start at a multiple of the list's size. The patch uses the general error "start register out of range" when this constraint isn't met, rather than an error specifically about multiples. This ensures that the error is consistent between these simple consecutive lists and later strided lists, for which the requirements aren't a simple multiple.
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford1-0/+5
SME2 adds a new format for the existing SVE predicate registers: predicates as counters rather than predicates as masks. In assembly code, operands that interpret predicates as counters are written pn<N> rather than p<N>. This patch adds support for these registers and extends some existing instructions to support them. Since the new forms are just a programmer convenience, there's no need to make them more restrictive than the earlier predicate-as-mask forms.
2023-03-30aarch64; Add support for vector offset rangesRichard Sandiford1-4/+19
Some SME2 instructions operate on a range of consecutive ZA vectors. This is indicated by syntax such as: za[<Wv>, <imml>:<immh>] Like with the earlier vgx2 and vgx4 support, we get better error messages if the parser allows all ZA indices to have a range. We can then reject invalid cases during constraint checking.
2023-03-30aarch64: Add support for vgx2 and vgx4Richard Sandiford1-0/+13
Many SME2 instructions operate on groups of 2 or 4 ZA vectors. This is indicated by adding a "vgx2" or "vgx4" group size to the ZA index. The group size is optional in assembly but preferred for disassembly. There is not a binary distinction between mnemonics that have group sizes and mnemonics that don't, nor between mnemonics that take vgx2 and mnemonics that take vgx4. We therefore get better error messages if we allow any ZA index to have a group size during parsing, and wait until constraint checking to reject invalid sizes. A quirk of the way errors are reported means that if an instruction is wrong both in its qualifiers and its use of a group size, we'll print suggested alternative instructions that also have an incorrect group size. But that's a general property that also applies to things like out-of-range immediates. It's also not obviously the wrong thing to do. We need to be relatively confident that we're looking at the right opcode before reporting detailed operand-specific errors, so doing qualifier checking first seems resonable.
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-3/+3
SME2 adds various new fields that are similar to AARCH64_OPND_SME_ZA_array, but are distinguished by the size of their offset fields. This patch adds _off4 to the name of the field that we already have.
2023-03-30aarch64: Add +sme2Richard Sandiford1-0/+1
This patch adds bare-bones support for +sme2. Later patches fill in the rest.
2023-03-30aarch64: Add support for strided register listsRichard Sandiford1-12/+26
SME2 has instructions that accept strided register lists, such as { z0.s, z4.s, z8.s, z12.s }. The purpose of this patch is to extend binutils to support such lists. The parsing code already had (unused) support for strides of 2. The idea here is instead to accept all strides during parsing and reject invalid strides during constraint checking. The SME2 instructions that accept strided operands also have non-strided forms. The errors about invalid strides therefore take a bitmask of acceptable strides, which allows multiple possibilities to be summed up in a single message. I've tried to update all code that handles register lists.
2023-03-30aarch64: Add a aarch64_cpu_supports_inst_p helperRichard Sandiford1-0/+3
Quite a lot of SME2 instructions have an opcode bit that selects between 32-bit and 64-bit forms of an instruction, with the 32-bit forms being part of base SME2 and with the 64-bit forms being part of an optional extension. It's nevertheless useful to have a single opcode entry for both forms since (a) that matches the ISA definition and (b) it tends to improve error reporting. This patch therefore adds a libopcodes function called aarch64_cpu_supports_inst_p that tests whether the target supports a particular instruction. In future it will depend on internal libopcodes routines.
2023-03-30aarch64: Add an operand class for SVE register listsRichard Sandiford1-0/+1
SVE register lists were classified as SVE_REG, since there had been no particular reason to separate them out. However, some SME2 instructions have tied register list operands, and so we need to distinguish registers and register lists when checking whether two operands match. Also, the register list operands used a general error message, even though we already have a dedicated error code for register lists that are the wrong length.
2023-03-30aarch64: Add an error code for out-of-range registersRichard Sandiford1-1/+9
libopcodes currently reports out-of-range registers as a general AARCH64_OPDE_OTHER_ERROR. However, this means that each register range needs its own hard-coded string, which is a bit cumbersome if the range is determined programmatically. This patch therefore adds a dedicated error type for out-of-range errors.
2023-03-30aarch64: Deprioritise AARCH64_OPDE_REG_LISTRichard Sandiford1-5/+9
SME2 has many instructions that take a list of SVE registers. There are often multiple forms, with different forms taking different numbers of registers. This means that if, after a successful parse and qualifier match, we find that the number of registers does not match the opcode entry, the associated error should have a lower priority/severity than other errors reported at the same stage. For example, if there are 2-register and 4-register forms of an instruction, and if the assembly code uses the 2-register form with an out-of-range value, the out-of-range value error against the 2-register instruction should have a higher priority than the "wrong number of registers" error against the 4-register instruction. This is tested by the main SME2 patches, but seemed worth splitting out.
2023-03-30aarch64: Update operand_mismatch_kind_namesRichard Sandiford1-1/+4
The contents of operand_mismatch_kind_names were out of sync with the enum.
2023-03-30aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford1-0/+1
This patch moves the range checks on ZA vector select offsets from gas to libopcodes. Doing the checks there means that the error messages contain the expected range. It also fits in better with the error severity scheme, which becomes important later. (This is because out-of-range indices are treated as more severe than syntax errors, on the basis that parsing must have succeeded if we get to the point of checking the completed opcode.) The patch also adds a new check_za_access function for checking ZA accesses. That's a bit over the top for one offset check, but the function becomes more complex with later patches. sme-9-illegal.s checked for an invalid .q suffix using: psel p1, p15, p3.q[w15] but this is doubly invalid because it misses the immediate part of the index. The patch keeps that test but adds another with a zero index, so that .q is the only thing wrong. The aarch64-tbl.h change includes neatening up the backslash positions.
2023-03-30aarch64: Make indexed_za use 64-bit immediatesRichard Sandiford1-1/+1
A later patch moves the range checking for ZA vector select offsets from gas to libopcodes. That in turn requires the immediate field to be big enough to support all parsed values. This shouldn't be a particularly size-sensitive structure, so there should be no memory problems with doing this.
2023-03-30aarch64: Rename za_tile_vector to za_indexRichard Sandiford1-10/+13
za_tile_vector is also used for indexing ZA as a whole, rather than just for indexing tiles. The former is more common than the latter in SME2, so this patch generalises the name to "indexed_za". The patch also names the associated structure, so that later patches can reuse it during parsing.
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