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authorRichard Sandiford <richard.sandiford@arm.com>2023-03-30 11:09:11 +0100
committerRichard Sandiford <richard.sandiford@arm.com>2023-03-30 11:09:11 +0100
commit90cd80f8c24f9919a10117aa93fc570ac8b7767a (patch)
treee7e09d8b6a357141301ea3184ff0eabfb1bb532a /include
parentabd542a2f1e15303ea4a9bf05d1a937b5162df5e (diff)
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aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array
SME2 adds various new fields that are similar to AARCH64_OPND_SME_ZA_array, but are distinguished by the size of their offset fields. This patch adds _off4 to the name of the field that we already have.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/aarch64.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 5c9b5e5..9458466 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -487,11 +487,11 @@ enum aarch64_opnd
AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */
AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */
AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */
- AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
- AARCH64_OPND_SME_ZA_array, /* SME ZA[<Wv>{, #<imm>}]. */
+ AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
+ AARCH64_OPND_SME_ZA_array_off4, /* SME ZA[<Wv>{, #<imm>}]. */
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
- AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
+ AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */