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authorPhilipp Tomsich <philipp.tomsich@vrull.eu>2023-04-26 14:09:34 -0600
committerJeff Law <jlaw@ventanamicro>2023-04-26 14:09:34 -0600
commit1656d3f8ef56a16745689c03269412988ebcaa54 (patch)
treeb329b8cd37a07f85f718ba3fbf1f2a0e8c2c8893 /include
parentdcdec68b0b5371c700bc6152de9c20eb1bdfa287 (diff)
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RISC-V: Support XVentanaCondOps extension
Ventana Micro has published the specification for their XVentanaCondOps ("conditional ops") extension at https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf which contains two new instructions - vt.maskc - vt.maskcn that can be used in constructing branchless sequences for various conditional-arithmetic, conditional-logical, and conditional-select operations. To support such vendor-defined instructions in the mainline binutils, this change also adds a riscv_supported_vendor_x_ext secondary dispatch table (but also keeps the behaviour of allowing any unknow X-extension to be specified in addition to the known ones from this table). As discussed, this change already includes the planned/agreed future requirements for X-extensions (which are likely to be captured in the riscv-toolchain-conventions repository): - a public specification document is available (see above) and is referenced from the gas-documentation - the naming follows chapter 27 of the RISC-V ISA specification - instructions are prefixed by a vendor-prefix (vt for Ventana) to ensure that they neither conflict with future standard extensions nor clash with other vendors bfd/ChangeLog: * elfxx-riscv.c (riscv_get_default_ext_version): Add riscv_supported_vendor_x_ext. (riscv_multi_subset_supports): Recognize INSN_CLASS_XVENTANACONDOPS. gas/ChangeLog: * doc/c-riscv.texi: Add section to list custom extensions and their documentation URLs. * testsuite/gas/riscv/x-ventana-condops.d: New test. * testsuite/gas/riscv/x-ventana-condops.s: New test. include/ChangeLog: * opcode/riscv-opc.h Add vt.maskc and vt.maskcn. * opcode/riscv.h (enum riscv_insn_class): Add INSN_CLASS_XVENTANACONDOPS. opcodes/ChangeLog: * riscv-opc.c: Add vt.maskc and vt.maskcn. Series-version: 1 Series-to: binutils@sourceware.org Series-cc: Kito Cheng <kito.cheng@sifive.com> Series-cc: Nelson Chu <nelson.chu@sifive.com> Series-cc: Greg Favor <gfavor@ventanamicro.com> Series-cc: Christoph Muellner <cmuellner@gcc.gnu.org>
Diffstat (limited to 'include')
-rw-r--r--include/opcode/riscv-opc.h8
-rw-r--r--include/opcode/riscv.h1
2 files changed, 9 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 85d35c1..91e56c0 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2342,6 +2342,11 @@
#define MASK_TH_SYNC_IS 0xffffffff
#define MATCH_TH_SYNC_S 0x0190000b
#define MASK_TH_SYNC_S 0xffffffff
+/* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
+#define MATCH_VT_MASKC 0x607b
+#define MASK_VT_MASKC 0xfe00707f
+#define MATCH_VT_MASKCN 0x707b
+#define MASK_VT_MASKCN 0xfe00707f
/* Unprivileged Counter/Timers CSR addresses. */
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
@@ -3236,6 +3241,9 @@ DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC)
DECLARE_INSN(th_sync_i, MATCH_TH_SYNC_I, MASK_TH_SYNC_I)
DECLARE_INSN(th_sync_is, MATCH_TH_SYNC_IS, MASK_TH_SYNC_IS)
DECLARE_INSN(th_sync_s, MATCH_TH_SYNC_S, MASK_TH_SYNC_S)
+/* XVentanaCondOps instructions. */
+DECLARE_INSN(vt_maskc, MATCH_VT_MASKC, MASK_VT_MASKC)
+DECLARE_INSN(vt_maskcn, MATCH_VT_MASKCN, MASK_VT_MASKCN)
#endif /* DECLARE_INSN */
#ifdef DECLARE_CSR
/* Unprivileged Counter/Timers CSRs. */
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b4ae552..e86a1bd 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -422,6 +422,7 @@ enum riscv_insn_class
INSN_CLASS_XTHEADMEMIDX,
INSN_CLASS_XTHEADMEMPAIR,
INSN_CLASS_XTHEADSYNC,
+ INSN_CLASS_XVENTANACONDOPS,
};
/* This structure holds information for a particular instruction. */