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| author | Maciej W. Rozycki <macro@orcam.me.uk> | 2023-06-15 04:45:03 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@orcam.me.uk> | 2023-06-15 04:45:03 +0100 |
| commit | 0c5c669cefa7aea782abe98d5455cb7f54bbe944 (patch) | |
| tree | ce2e5e24b48098a877a4965a0cd81a7869290bf9 /include | |
| parent | 9cfee3962cfbd19dae5cc0087b43be4b276795e7 (diff) | |
| download | gdb-0c5c669cefa7aea782abe98d5455cb7f54bbe944.zip gdb-0c5c669cefa7aea782abe98d5455cb7f54bbe944.tar.gz gdb-0c5c669cefa7aea782abe98d5455cb7f54bbe944.tar.bz2 | |
Revert "MIPS: add MT ASE support for micromips32"
This reverts commit acce83dacff0ce43677410c67aaae32817afe991. It was
applied unapproved.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/mips.h | 35 |
1 files changed, 10 insertions, 25 deletions
diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 666ddae..75d3fc2 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -2106,8 +2106,6 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_SH_SA3 13 #define MICROMIPSOP_MASK_SA4 0xf #define MICROMIPSOP_SH_SA4 12 -#define MICROMIPSOP_MASK_SA5 0x1f -#define MICROMIPSOP_SH_SA5 11 #define MICROMIPSOP_MASK_IMM8 0xff #define MICROMIPSOP_SH_IMM8 13 #define MICROMIPSOP_MASK_IMM10 0x3ff @@ -2137,18 +2135,14 @@ extern const int bfd_mips16_num_opcodes; #define MICROMIPSOP_SH_DSPSFT_7 0 #define MICROMIPSOP_MASK_RDDSP 0 #define MICROMIPSOP_SH_RDDSP 0 -#define MICROMIPSOP_MASK_MT_U 0x1 -#define MICROMIPSOP_SH_MT_U 10 -#define MICROMIPSOP_MASK_MT_H 0x1 -#define MICROMIPSOP_SH_MT_H 9 -#define MICROMIPSOP_MASK_MTACC_T 0x3 -#define MICROMIPSOP_SH_MTACC_T 23 -#define MICROMIPSOP_MASK_MTACC_S 0x3 -#define MICROMIPSOP_SH_MTACC_S 18 -#define MICROMIPSOP_MASK_MT_SEL 0x7 /* The sel field of mftr and mttr. */ -#define MICROMIPSOP_SH_MT_SEL 4 -#define MICROMIPSOP_MASK_MT_RX 0x1f -#define MICROMIPSOP_SH_MT_RX 11 +#define MICROMIPSOP_MASK_MT_U 0 +#define MICROMIPSOP_SH_MT_U 0 +#define MICROMIPSOP_MASK_MT_H 0 +#define MICROMIPSOP_SH_MT_H 0 +#define MICROMIPSOP_MASK_MTACC_T 0 +#define MICROMIPSOP_SH_MTACC_T 0 +#define MICROMIPSOP_MASK_MTACC_D 0 +#define MICROMIPSOP_SH_MTACC_D 0 #define MICROMIPSOP_MASK_BBITIND 0 #define MICROMIPSOP_SH_BBITIND 0 #define MICROMIPSOP_MASK_CINSPOS 0 @@ -2304,8 +2298,7 @@ extern const int bfd_mips16_num_opcodes; Coprocessor instructions: "E" 5-bit target register (MICROMIPSOP_*_RT) "G" 5-bit source register (MICROMIPSOP_*_RS) - "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL), not for MTTR and MFTR - "e" 5-bit control target register (MICROMIPSOP_*_RT) + "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) "g" 5-bit control source register (MICROMIPSOP_*_RS) Macro instructions: @@ -2326,7 +2319,7 @@ extern const int bfd_mips16_num_opcodes; "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) - "^" 5-bit unsigned immediate (MICROMIPSOP_*_SA5) + "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) microMIPS Enhanced VA Scheme: "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) @@ -2358,14 +2351,6 @@ extern const int bfd_mips16_num_opcodes; "+*" 5-bit register vector element index at bit 16 "+|" 8-bit mask at bit 16 - microMIPS MT ASE usage: - "!" 1-bit usermode flag (MICROMIPSOP_*_MT_U) - "$" 1-bit load high flag (MICROMIPSOP_*_MT_H) - "*" 2-bit dsp accumulator register (MICROMIPSOP_*_MTACC_T) - "&" 2-bit dsp accumulator register (MICROMIPSOP_*_MTACC_S) - "?" 3-bit MFTR and MTTR sel (MICROMIPSOP_SH_MT_SEL) - "+t" 5-bit control rx register (MICROMIPSOP_*_MT_RX) - Other: "()" parens surrounding optional value "," separates operands |