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path: root/include/opcode/riscv.h
AgeCommit message (Expand)AuthorFilesLines
2024-06-28RISC-V: Add Zabha extension CAS instructions.Jiawei1-0/+1
2024-06-18RISC-V: Add SiFive cease extension v1.0Hau Hsu1-0/+1
2024-06-18RISC-V: Support Zacas extension.Gianluca Guida1-0/+1
2024-06-06RISC-V: Add support for Zvfbfwma extensionXiao Zeng1-0/+1
2024-06-06RISC-V: Add support for Zvfbfmin extensionXiao Zeng1-0/+1
2024-06-06RISC-V: Add support for Zfbfmin extensionXiao Zeng1-0/+1
2024-06-05RISC-V: Add support for XCVmem extension in CV32E40PMary Bennett1-0/+1
2024-06-05RISC-V: Add support for XCVbi extension in CV32E40PMary Bennett1-0/+4
2024-06-05RISC-V: Add support for XCVelw extension in CV32E40PMary Bennett1-0/+1
2024-05-08RISC-V: Support B, Zaamo and Zalrsc extensions.Nelson Chu1-1/+2
2024-04-09RISC-V: Support Zcmp push/pop instructions.Jiawei1-0/+18
2024-03-08RISC-V: Support Zabha extension.Jiawei1-0/+1
2024-01-05RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvliJin Ma1-0/+11
2024-01-04Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2023-12-01RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0Nelson Chu1-0/+7
2023-12-01RISC-V: Zv*: Add support for Zvkb ISA extensionChristoph Müllner1-0/+1
2023-11-24RISC-V: reduce redundancy in sign/zero extension macro insn handlingJan Beulich1-2/+1
2023-11-23RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extensionJin Ma1-0/+1
2023-11-23RISC-V: Add T-Head VECTOR vendor extension.Jin Ma1-0/+1
2023-11-07RISC-V: Add support for XCValu extension in CV32E40PMary Bennett1-0/+5
2023-11-07RISC-V: Add support for XCVmac extension in CV32E40PMary Bennett1-0/+7
2023-11-03RISC-V: reduce redundancy in load/store macro insn handlingJan Beulich1-19/+3
2023-09-05RISC-V: fold duplicate code in vector_macro()Jan Beulich1-1/+0
2023-08-15RISC-V: Make "fli.h" available to 'Zvfh' + 'Zfa'Tsukasa OI1-0/+1
2023-08-15RISC-V: Add support for the 'Zihintntl' extensionTsukasa OI1-0/+2
2023-08-15RISC-V: remove indirection from register tablesJan Beulich1-7/+9
2023-08-02Revert "2.41 Release sources"Sam James1-2/+14
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton1-14/+2
2023-07-18RISC-V: Supports Zcb extension.Jiawei1-0/+14
2023-07-03RISC-V: Zvkh[a,b]: Remove individual instruction classChristoph Müllner1-2/+0
2023-07-01RISC-V: Add support for the Zvksh ISA extensionChristoph Müllner1-0/+1
2023-07-01RISC-V: Add support for the Zvksed ISA extensionChristoph Müllner1-0/+1
2023-07-01RISC-V: Add support for the Zvknh[a,b] ISA extensionsChristoph Müllner1-0/+3
2023-07-01RISC-V: Add support for the Zvkned ISA extensionChristoph Müllner1-0/+1
2023-07-01RISC-V: Add support for the Zvkg ISA extensionChristoph Müllner1-0/+1
2023-07-01RISC-V: Add support for the Zvbc extensionNathan Huckleberry1-0/+1
2023-07-01RISC-V: Add support for the Zvbb ISA extensionChristoph Müllner1-0/+5
2023-06-30RISC-V: Add support for the Zfa extensionChristoph Müllner1-0/+6
2023-06-27 RISC-V: Support Zicond extensionPhilipp Tomsich1-0/+1
2023-06-01RISC-V: PR30449, Add lga assembler macro support.Jim Wilson1-0/+1
2023-04-26 RISC-V: Support XVentanaCondOps extensionPhilipp Tomsich1-0/+1
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-11-17RISC-V: Add T-Head Int vendor extensionChristoph Müllner1-0/+1
2022-11-17RISC-V: Add T-Head Fmv vendor extensionChristoph Müllner1-0/+1
2022-10-14RISC-V: Move certain arrays to riscv-opc.cTsukasa OI1-11/+2
2022-10-04RISC-V: Fix buffer overflow on print_insn_riscvTsukasa OI1-0/+2
2022-10-04RISC-V: Renamed INSN_CLASS for floating point in integer extensions.Nelson Chu1-7/+7
2022-10-04RISC-V/gas: allow generating up to 176-bit instructions with .insnJan Beulich1-0/+3
2022-09-23RISC-V: Add Zawrs ISA extension supportChristoph Müllner1-0/+1
2022-09-22RISC-V: Add T-Head MemPair vendor extensionChristoph Müllner1-0/+1