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| author | Nathan Huckleberry <nhuck@google.com> | 2023-06-30 22:43:40 +0200 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro> | 2023-07-01 07:28:34 -0600 |
| commit | c0a98a853d5ccde35dca20ad5d7cea0a70e16d56 (patch) | |
| tree | 5a5c318686f441523224c6657ee51419069c38ff /include/opcode/riscv.h | |
| parent | c8cb37347fde3ae12c943c2133a1043eece4c127 (diff) | |
| download | gdb-c0a98a853d5ccde35dca20ad5d7cea0a70e16d56.zip gdb-c0a98a853d5ccde35dca20ad5d7cea0a70e16d56.tar.gz gdb-c0a98a853d5ccde35dca20ad5d7cea0a70e16d56.tar.bz2 | |
RISC-V: Add support for the Zvbc extension
Zvbc is part of the crypto vector extensions.
This extension adds the following instructions:
- vclmul.[vv,vx]
- vclmulh.[vv,vx]
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvbc.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* testsuite/gas/riscv/zvbc.d: New test.
* testsuite/gas/riscv/zvbc.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VCLMUL_VV): New.
(MASK_VCLMUL_VV): New.
(MATCH_VCLMUL_VX): New.
(MASK_VCLMUL_VX): New.
(MATCH_VCLMULH_VV): New.
(MASK_VCLMULH_VV): New.
(MATCH_VCLMULH_VX): New.
(MASK_VCLMULH_VX): New.
(DECLARE_INSN): New.
* opcode/riscv.h (enum riscv_insn_class): Add instruction class
support for Zvbc.
opcodes/ChangeLog:
* riscv-opc.c: Add Zvbc instruction.
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include/opcode/riscv.h')
| -rw-r--r-- | include/opcode/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 4878564..783b1c0 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -415,6 +415,7 @@ enum riscv_insn_class INSN_CLASS_V, INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, + INSN_CLASS_ZVBC, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, |