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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-11-13 16:59:21 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2022-11-17 16:43:55 +0800 |
| commit | 01804a098dea7d08857eee82bcaad04676dd8ea1 (patch) | |
| tree | 69ec5662e29df0e9632fca8f788acb0383440ef2 /include/opcode/riscv.h | |
| parent | 4a3bc79bf4c0e89c876c930a1e95a02213277460 (diff) | |
| download | gdb-01804a098dea7d08857eee82bcaad04676dd8ea1.zip gdb-01804a098dea7d08857eee82bcaad04676dd8ea1.tar.gz gdb-01804a098dea7d08857eee82bcaad04676dd8ea1.tar.bz2 | |
RISC-V: Add T-Head Int vendor extension
This patch adds the XTheadInt extension, which provides interrupt
stack management instructions.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include/opcode/riscv.h')
| -rw-r--r-- | include/opcode/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index f90cf97..c3cbde6 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -417,6 +417,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADCONDMOV, INSN_CLASS_XTHEADFMEMIDX, INSN_CLASS_XTHEADFMV, + INSN_CLASS_XTHEADINT, INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, |