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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-11-13 16:59:20 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2022-11-17 16:43:49 +0800 |
| commit | 4a3bc79bf4c0e89c876c930a1e95a02213277460 (patch) | |
| tree | 4a82c5fbaf454ec2fcf147c1134d67b2f38d5879 /include/opcode/riscv.h | |
| parent | 7a4ce4a1bcff9710b7dede9797e6d5eb2364c06e (diff) | |
| download | gdb-4a3bc79bf4c0e89c876c930a1e95a02213277460.zip gdb-4a3bc79bf4c0e89c876c930a1e95a02213277460.tar.gz gdb-4a3bc79bf4c0e89c876c930a1e95a02213277460.tar.bz2 | |
RISC-V: Add T-Head Fmv vendor extension
This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include/opcode/riscv.h')
| -rw-r--r-- | include/opcode/riscv.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index dddabfd..f90cf97 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -416,6 +416,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADCMO, INSN_CLASS_XTHEADCONDMOV, INSN_CLASS_XTHEADFMEMIDX, + INSN_CLASS_XTHEADFMV, INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADMEMIDX, INSN_CLASS_XTHEADMEMPAIR, |