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AgeCommit message (Expand)AuthorFilesLines
2022-05-28Permit mtval to be zero in misaligned address test, fixes #389 (#390)Luke Wren1-0/+2
2022-03-08Add Zfh and Svnapot to Spike ISA stringAndrew Waterman1-2/+2
2021-07-22Fix #352 (#353)Daniel Lustig1-2/+2
2021-07-21Move the Svnapot test to its own folder (#351)Daniel Lustig4-1/+10
2021-07-19Add a test for Svnapot (#349)Daniel Lustig2-0/+173
2021-06-01Enable access to cycle counter before trying to write itAndrew Waterman1-0/+13
2021-06-01Test all four ways of reading a read-only CSRAndrew Waterman1-0/+8
2021-05-12Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: (#...SLAMET RIANTO2-0/+2
2021-05-10Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support C...SLAMET RIANTO3-0/+52
2021-02-01Align mtvec in rv32mi-p-shamt testAndrew Waterman1-0/+1
2021-01-08Don't rely on the implementation-specific WFI time limit (#318)Paul Donahue1-18/+0
2021-01-04Disable rv32ua/rv64ua LR/SC test case 4 (#316)Ben Marshall1-8/+14
2020-12-16Refactor rv64ud structural test to match format of other tests (#311)Kathlene Hurt1-11/+13
2020-12-08Add rd=x0 test case to csr test (#308)Takahiro1-0/+1
2020-12-07Fix minor typo (#307)Takahiro1-1/+1
2020-11-20Only attempt to build tests supported by compilerAndrew Waterman19-38/+6
2020-11-11add zfh (float16) test case and related macros (#301)Chih-Min Chao26-0/+769
2020-10-19use registers present on rv32e (#299)Sandeep Rajendran1-4/+4
2020-03-21Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5Andrew Waterman1-7/+7
2020-03-21Move self-modifying 'fence.i' ops to .data memory section (#269)WRansohoff1-6/+14
2020-03-19Fix comments error in fmin.S (#267)Mohanson2-4/+4
2020-03-18Have both rs=rd and rs!=rd cases in csr.S (#263)Takahiro1-12/+15
2020-03-18Fix shamt.S header (#264)Takahiro1-2/+2
2020-03-16Add a test case rs = rd to jalr.S (#258)Takahiro1-0/+16
2020-03-11Add comment explaining convoluted rv64mi-p-scall behaviorAndrew Waterman1-0/+6
2020-03-11Revert "scall: make the intention of the test in machine mode more clear (#246)"Andrew Waterman1-6/+1
2020-03-11Setup a multilevel page table to avoid misaligned superpages caused by variab...Cedric Orban1-0/+4
2020-03-06Don't assume reset state of mscratch (#254)Paul Donahue1-1/+1
2020-03-02enable rv32e compatability by replacing reg x29 with reg x7 (#250)Cedric Orban1-12/+12
2020-02-21scall: make the intention of the test in machine mode more clear (#246)Nils Asmussen1-1/+6
2020-02-20Fix rv64mi-p-csr on systems with FPUsAndrew Waterman1-2/+3
2020-01-31Added CSR test cases on whether writing 0 to CSR works, as that might get ove...Torbjørn Viem Ness1-0/+2
2019-11-04Remove cruft from icache-alias testAndrew Waterman1-35/+0
2019-11-04Add rv64si-p-icache-aliasAndrew Waterman2-0/+177
2019-07-29Support RV32E. Fixed #198 (#200)Leway Colin3-42/+42
2019-04-20masking no longer required.Neel1-16/+0
2019-04-20removing check for reset value of type in mcontrolNeel1-10/+8
2019-04-20fix for #159 #158Neel1-4/+7
2019-03-17Rename TEST_SRL to TEST_SRLI to avoid conflicts with another TEST_SRL (#183)Pavel I. Kryukov1-18/+18
2019-01-26Fix comments for shift amount. (#177)takeoverjp3-3/+3
2018-12-18Avoid using t3 and t4 for supporting RV32E (#173)zhonghochen1-5/+6
2018-11-16Test memory content on failing SC (#171)Florian Zaruba1-4/+10
2018-09-08RV64 s{ll,ra,rl}w tests with non-canonical valuesTommy Thorn6-0/+42
2018-09-06Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) ...Andrew Waterman1-1/+1
2018-09-06breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)Tommy Thorn1-1/+1
2018-08-21Changing the register mstatus is read into (#152)Srivatsa Yogendra1-2/+2
2018-08-20Revert "Fix to solve the failing tests shamt, csr and scall (#151)"Andrew Waterman2-52/+5
2018-08-17Fix to solve the failing tests shamt, csr and scall (#151)Srivatsa Yogendra2-5/+52
2018-08-17making mtvec_handler global (#150)Srivatsa Yogendra1-0/+1
2018-07-09Check that SC yields the load reservationAndrew Waterman1-0/+9
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