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See: https://www.kernel.org/doc/html/latest/arch/riscv/hwprobe.html
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It was originally added as a temporary hack to hide a race condition in
a prototype. It should've been removed long ago.
Resolves #312
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config (#98)""
This reverts commit 7ae86fb97b792586493255f935f2f12ff068b13f.
This will continue to allow accesses to cycle/time via mcycle/mtime
despite https://github.com/riscv-software-src/riscv-isa-sim/pull/1297.
The hope is this will keep most people happy while doing the right thing
with Spike.
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The UART drivers all return -1 if no character is present, and so that's
what we should do if there's no UART at all.
See discussion on https://github.com/riscv-non-isa/riscv-sbi-doc/issues/82
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h/t @jrtc27
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This reverts commit fd2ddce557a9085ccdba1a455eded4808e7466c6.
The SBI took a different approach (explicit SBI call) to support writing
the counters, rather than using traps.
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Resolves #249
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Also use pointer arithmetic on char * instead of void *.
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This reverts commit 5450c2f731f16abe3a4f244c383c55f559c97359.
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This reverts commit 717702ceec053afd424a41ef6a4078d3cbd755b8.
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This reverts commit 17bec41e9bd44c43901938b784680661b9b28a76.
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Also use pointer arithmetic on char * instead of void *.
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This reverts commit 0d1fdc2e24b7b6247a55d24c13ae85dca7f45695.
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clang only supports register variables if they are declared globally.
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This reverts commit e8d15a489fa76612707ff9e99feb0fb36acc9f14.
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Use of asm aliased register variables in local scope can only be used
for extended assembly parameters. This changes the few instances of
this in the floating point emulation to use the GNU extended assembly
syntax to access the `tp` register. This ensures that we do not rely on
undefined behaviour. This was uncovered when building the Proxy kernel
with clang and LLVM.
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The use of `asm` for register aliasing is supported in two different
contexts:
- local variables (including GNU expression statements) where it may
only be used for specifying registers for input and output operands to
extended `asm` syntax.
c.f. https://gcc.gnu.org/onlinedocs/gcc/Local-Register-Variables.html#Local-Register-Variables
- global variables where it may be used to observe the contents of a
register.
c.f. https://gcc.gnu.org/onlinedocs/gcc/Global-Register-Variables.html#Global-Register-Variables
The two options here is to either to hoist the variable out into a
global variable, but then it should not be in a header due to fears of
ODR in case the optimizer does not inline it away, and thus becomes a
bit more tricky. The alternative that this change actually adopts is to
explicitly use a move to copy the value out via the GNU extended
assembly syntax.
With this change, it is now possible to build the Proxy Kernel
completely with clang/LLVM and link with LLD. The generated kernel also
runs under SPIKE and behaves as expected in a simple smoke test (without
any executable prints the expected message, and runs a trivial RVV
example).
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This is an equivalent rewrite of the existing code. When building with
gas, the `bltu` would implicitly get relaxed to the `bgeu` + `j`. This
relaxation is required as the `init_other_hart` is not guaranteed to be
addressable in 12-bits. When building with the LLVM IAS instead of gas
we fail to link as the branch is not relaxed. This change enables LLVM
to build and link this code with the LLVM IAS and lld.
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The LLVM IAS currently does not support the older spelling for the CSR.
Update the references to the modern name.
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The LLVM IAS does not support the older name for the `mtval` CSR. This
updates the name to the current spelling, which is required to build
with the LLVM IAS. This remains compatible with binutils as well.
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This replaces use of the old `sbadaddr` CSR name with the current
`stval` name. The old spelling is not supported by the LLVM IAS,
however, the modern spelling is supported by both LLVM and binutils.
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Using recent compilers we get the following error message:
../pk/pk.c: In function 'run_loaded_program.constprop':
../pk/pk.c:177:3: error: both arguments to '__builtin___clear_cache'
must be pointers
177 | __clear_cache(0, 0);
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Let's use the existing function __riscv_flush_icache(),
give it a header with a prototype and use it to
emits the FENCE.I instruction directly.
See #239
Suggested-by: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Christoph Muellner <cmuellner@linux.com>
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The upstream LiteX project defaults to "litex,liteuart" as the value
for the "compatible" property of the UART DT node, so let's add it to
the current list of accepted strings.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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Tested using the RocketChip CPU option.
(see https://github.com/enjoy-digital/litex)
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
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* add device tree in elf, using --with-dts to add the absolute path of device tree
* Disable device tree filter
* Remove *.dtb dependence, when the --with-dts option is not used
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This reverts commit a161e6f3ef31004e47a5b94b85c2e84b764f8637.
Resolves #218
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* add device tree in elf, using --with-dts to add the absolute path of device tree
* Disable device tree filter
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Recent QEMU will fault for 8-byte accesses. Use a uint32_t instead of
uintptr_t to avoid those problems.
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While it's unused upstream, according to the SiFive FU540 document, the
UART divisor register is at offset 0x18.
This also maps the interrupt enable and interrupt pending register
offsets.
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QEMU's finisher is "sifive,test1\0sifive,test0\0syscon" so we fail to
detect it currently. Instead, search the entire list, and for
completeness do the same with the HTIF and SiFive UART drivers.
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- Update to riscv-opcodes/231c5d58940113b006aa9fa22f47c18d5fac4123
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Some ELF loaders, in particular gdb's load command for dynamically
loading files into memory, which is often used to load binaries onto
FPGAs over JTAG, do not zero out BSS, leaving the memory in whatever
state it was previously in. Thus, introduce a new --enable-zero-bss
configure flag, which will include code to zero out BSS when booting.
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77a5df569451571d608650a34183d53df99790ec)
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