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author | Marcus Comstedt <marcus@mc.pp.se> | 2021-06-16 22:49:50 +0200 |
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committer | GitHub <noreply@github.com> | 2021-06-16 13:49:50 -0700 |
commit | ae7348b246bc091f5af844a7bdaf1044cac90635 (patch) | |
tree | 7c729bfdf5e1b53c4be56188d815e08cd3a932f8 /machine | |
parent | e8e6b3aaee44d43b48164fbd377864c3a682dbd3 (diff) | |
download | riscv-pk-ae7348b246bc091f5af844a7bdaf1044cac90635.zip riscv-pk-ae7348b246bc091f5af844a7bdaf1044cac90635.tar.gz riscv-pk-ae7348b246bc091f5af844a7bdaf1044cac90635.tar.bz2 |
Set desired endianness at boot time (#247)
Diffstat (limited to 'machine')
-rw-r--r-- | machine/mentry.S | 11 | ||||
-rw-r--r-- | machine/minit.c | 16 |
2 files changed, 27 insertions, 0 deletions
diff --git a/machine/mentry.S b/machine/mentry.S index e71745c..4cf9685 100644 --- a/machine/mentry.S +++ b/machine/mentry.S @@ -255,6 +255,17 @@ do_reset: li x31, 0 csrw mscratch, x0 +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + # fixup endianness before making any loads or stores +#if __riscv_xlen == 32 + li t0, MSTATUSH_MBE + csrs CSR_MSTATUSH, t0 +#else + li t0, MSTATUS_MBE + csrs CSR_MSTATUS, t0 +#endif +#endif + # write mtvec and make sure it sticks la t0, trap_vector csrw mtvec, t0 diff --git a/machine/minit.c b/machine/minit.c index c519926..d35f9df 100644 --- a/machine/minit.c +++ b/machine/minit.c @@ -24,6 +24,19 @@ void* kernel_end; static void mstatus_init() { uintptr_t mstatus = 0; +#if __riscv_xlen == 32 + uint32_t mstatush = 0; +#endif + + // Set endianness +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#if __riscv_xlen == 32 + mstatush |= MSTATUSH_SBE | MSTATUSH_MBE; +#else + mstatus |= MSTATUS_SBE | MSTATUS_MBE; +#endif + mstatus |= MSTATUS_UBE; +#endif // Enable FPU if (supports_extension('F')) @@ -34,6 +47,9 @@ static void mstatus_init() mstatus |= MSTATUS_VS; write_csr(mstatus, mstatus); +#if __riscv_xlen == 32 && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ + write_csr(0x310, mstatush); /* mstatush is not known to gas */ +#endif // Enable user/supervisor use of perf counters if (supports_extension('S')) |