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| author | Andrew Waterman <andrew@sifive.com> | 2021-08-04 16:40:23 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2021-08-04 16:40:23 -0700 |
| commit | 50b6b6cc28f7a7252bbd3841222d37737ce28451 (patch) | |
| tree | 923cbbc8a97d670bb7b13845caeb0f724cfe973e /machine | |
| parent | 18084da90157ddc7aa4448e5f216cf6a486a64c8 (diff) | |
| download | riscv-pk-50b6b6cc28f7a7252bbd3841222d37737ce28451.zip riscv-pk-50b6b6cc28f7a7252bbd3841222d37737ce28451.tar.gz riscv-pk-50b6b6cc28f7a7252bbd3841222d37737ce28451.tar.bz2 | |
Revert "Revert "Use a global 'tp' register.""
This reverts commit 717702ceec053afd424a41ef6a4078d3cbd755b8.
Diffstat (limited to 'machine')
| -rw-r--r-- | machine/fp_emulation.h | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/machine/fp_emulation.h b/machine/fp_emulation.h index 1352ca3..98e261d 100644 --- a/machine/fp_emulation.h +++ b/machine/fp_emulation.h @@ -10,6 +10,8 @@ #define PRECISION_S 0 #define PRECISION_D 1 +register long tp asm("tp"); + #ifdef __riscv_flen # define GET_F32_REG(insn, pos, regs) ({ \ register int32_t value asm("a0") = SHIFT_RIGHT(insn, (pos)-3) & 0xf8; \ @@ -41,20 +43,20 @@ # define SET_FFLAGS(value) write_csr(fflags, (value)) # define SETUP_STATIC_ROUNDING(insn) ({ \ - register long tp asm("tp") = read_csr(frm); \ + tp = read_csr(frm); \ if (likely(((insn) & MASK_FUNCT3) == MASK_FUNCT3)) ; \ else if (GET_RM(insn) > 4) return truly_illegal_insn(regs, mcause, mepc, mstatus, insn); \ else tp = GET_RM(insn); \ asm volatile ("":"+r"(tp)); }) # define softfloat_raiseFlags(which) set_csr(fflags, which) -# define softfloat_roundingMode ({ register int tp asm("tp"); tp; }) +# define softfloat_roundingMode ((int)tp) # define SET_FS_DIRTY() ((void) 0) #else # define GET_F64_REG(insn, pos, regs) (*(int64_t*)((void*)((regs) + 32) + (SHIFT_RIGHT(insn, (pos)-3) & 0xf8))) # define SET_F64_REG(insn, pos, regs, val) (GET_F64_REG(insn, pos, regs) = (val)) # define GET_F32_REG(insn, pos, regs) (*(int32_t*)&GET_F64_REG(insn, pos, regs)) # define SET_F32_REG(insn, pos, regs, val) (GET_F32_REG(insn, pos, regs) = (val)) -# define GET_FCSR() ({ register int tp asm("tp"); tp & 0xFF; }) +# define GET_FCSR() ({ (int)tp & 0xFF; }) # define SET_FCSR(value) ({ asm volatile("add tp, x0, %0" :: "rI"((value) & 0xFF)); SET_FS_DIRTY(); }) # define GET_FRM() (GET_FCSR() >> 5) # define SET_FRM(value) SET_FCSR(GET_FFLAGS() | ((value) << 5)) @@ -62,13 +64,13 @@ # define SET_FFLAGS(value) SET_FCSR((GET_FRM() << 5) | ((value) & 0x1F)) # define SETUP_STATIC_ROUNDING(insn) ({ \ - register int tp asm("tp"); tp &= 0xFF; \ + tp &= 0xFF; \ if (likely(((insn) & MASK_FUNCT3) == MASK_FUNCT3)) tp |= tp << 8; \ else if (GET_RM(insn) > 4) return truly_illegal_insn(regs, mcause, mepc, mstatus, insn); \ else tp |= GET_RM(insn) << 13; \ asm volatile ("":"+r"(tp)); }) # define softfloat_raiseFlags(which) ({ asm volatile ("or tp, tp, %0" :: "rI"(which)); }) -# define softfloat_roundingMode ({ register int tp asm("tp"); tp >> 13; }) +# define softfloat_roundingMode ({ (int)tp >> 13; }) # define SET_FS_DIRTY() set_csr(mstatus, MSTATUS_FS) #endif |