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author | Andrew Waterman <andrew@sifive.com> | 2023-03-27 15:57:42 -0700 |
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committer | Andrew Waterman <andrew@sifive.com> | 2023-03-27 15:58:43 -0700 |
commit | 3ed18cfbc707c75af83941e8fdf7f68f5a3b4803 (patch) | |
tree | 151c4a6304fd0ff3335128c30c9a4d7c02997f9b /machine | |
parent | 573c858d9071a2216537f71de651a814f76ee76d (diff) | |
download | riscv-pk-3ed18cfbc707c75af83941e8fdf7f68f5a3b4803.zip riscv-pk-3ed18cfbc707c75af83941e8fdf7f68f5a3b4803.tar.gz riscv-pk-3ed18cfbc707c75af83941e8fdf7f68f5a3b4803.tar.bz2 |
Revert "Revert "SBI emulation of reads and writes to perf counters and config (#98)""
This reverts commit 7ae86fb97b792586493255f935f2f12ff068b13f.
This will continue to allow accesses to cycle/time via mcycle/mtime
despite https://github.com/riscv-software-src/riscv-isa-sim/pull/1297.
The hope is this will keep most people happy while doing the right thing
with Spike.
Diffstat (limited to 'machine')
-rw-r--r-- | machine/emulation.c | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/machine/emulation.c b/machine/emulation.c index 6aad1a8..6b28a2d 100644 --- a/machine/emulation.c +++ b/machine/emulation.c @@ -162,18 +162,64 @@ static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result switch (num) { + case CSR_CYCLE: + if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1)) + return -1; + *result = read_csr(mcycle); + return 0; case CSR_TIME: if (!((counteren >> (CSR_TIME - CSR_CYCLE)) & 1)) return -1; *result = *mtime; return 0; + case CSR_INSTRET: + if (!((counteren >> (CSR_INSTRET - CSR_CYCLE)) & 1)) + return -1; + *result = read_csr(minstret); + return 0; + case CSR_MHPMCOUNTER3: + if (!((counteren >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1)) + return -1; + *result = read_csr(mhpmcounter3); + return 0; + case CSR_MHPMCOUNTER4: + if (!((counteren >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1)) + return -1; + *result = read_csr(mhpmcounter4); + return 0; #if __riscv_xlen == 32 + case CSR_CYCLEH: + if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1)) + return -1; + *result = read_csr(mcycleh); + return 0; case CSR_TIMEH: if (!((counteren >> (CSR_TIME - CSR_CYCLE)) & 1)) return -1; *result = *mtime >> 32; return 0; + case CSR_INSTRETH: + if (!((counteren >> (CSR_INSTRET - CSR_CYCLE)) & 1)) + return -1; + *result = read_csr(minstreth); + return 0; + case CSR_MHPMCOUNTER3H: + if (!((counteren >> (3 + CSR_MHPMCOUNTER3 - CSR_MHPMCOUNTER3)) & 1)) + return -1; + *result = read_csr(mhpmcounter3h); + return 0; + case CSR_MHPMCOUNTER4H: + if (!((counteren >> (3 + CSR_MHPMCOUNTER4 - CSR_MHPMCOUNTER3)) & 1)) + return -1; + *result = read_csr(mhpmcounter4h); + return 0; #endif + case CSR_MHPMEVENT3: + *result = read_csr(mhpmevent3); + return 0; + case CSR_MHPMEVENT4: + *result = read_csr(mhpmevent4); + return 0; #if !defined(__riscv_flen) && defined(PK_ENABLE_FP_EMULATION) case CSR_FRM: if ((mstatus & MSTATUS_FS) == 0) break; @@ -196,6 +242,18 @@ static inline int emulate_write_csr(int num, uintptr_t value, uintptr_t mstatus) { switch (num) { + case CSR_CYCLE: write_csr(mcycle, value); return 0; + case CSR_INSTRET: write_csr(minstret, value); return 0; + case CSR_MHPMCOUNTER3: write_csr(mhpmcounter3, value); return 0; + case CSR_MHPMCOUNTER4: write_csr(mhpmcounter4, value); return 0; +#if __riscv_xlen == 32 + case CSR_CYCLEH: write_csr(mcycleh, value); return 0; + case CSR_INSTRETH: write_csr(minstreth, value); return 0; + case CSR_MHPMCOUNTER3H: write_csr(mhpmcounter3h, value); return 0; + case CSR_MHPMCOUNTER4H: write_csr(mhpmcounter4h, value); return 0; +#endif + case CSR_MHPMEVENT3: write_csr(mhpmevent3, value); return 0; + case CSR_MHPMEVENT4: write_csr(mhpmevent4, value); return 0; #if !defined(__riscv_flen) && defined(PK_ENABLE_FP_EMULATION) case CSR_FRM: SET_FRM(value); return 0; case CSR_FFLAGS: SET_FFLAGS(value); return 0; |