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| author | James Clarke <jrtc27@jrtc27.com> | 2020-02-03 00:53:17 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-02 16:53:17 -0800 |
| commit | 2c4e689bc1ed4440d0d95b3b350ce872e7f75865 (patch) | |
| tree | 136e0fefebe6ec544c101b4e04bb56a85ede57f1 /machine | |
| parent | 6fa3555cc501ab1dfb034061e991e065e2e54253 (diff) | |
| download | riscv-pk-2c4e689bc1ed4440d0d95b3b350ce872e7f75865.zip riscv-pk-2c4e689bc1ed4440d0d95b3b350ce872e7f75865.tar.gz riscv-pk-2c4e689bc1ed4440d0d95b3b350ce872e7f75865.tar.bz2 | |
Support manually zeroing out BSS when booting (#188)
Some ELF loaders, in particular gdb's load command for dynamically
loading files into memory, which is often used to load binaries onto
FPGAs over JTAG, do not zero out BSS, leaving the memory in whatever
state it was previously in. Thus, introduce a new --enable-zero-bss
configure flag, which will include code to zero out BSS when booting.
Diffstat (limited to 'machine')
| -rw-r--r-- | machine/mentry.S | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/machine/mentry.S b/machine/mentry.S index 84bd3c1..9ec9916 100644 --- a/machine/mentry.S +++ b/machine/mentry.S @@ -267,9 +267,23 @@ do_reset: slli a2, a3, RISCV_PGSHIFT add sp, sp, a2 + bnez a3, .LmultiHartInit + +#ifdef ZERO_BSS + # Zero out BSS; linker script provides alignment and padding + la t0, _fbss + la t1, _end + beq t0, t1, 2f +1:STORE zero, 0(t0) + addi t0, t0, REGBYTES + bne t0, t1, 1b +2: +#endif + # Boot on the first hart - beqz a3, init_first_hart + j init_first_hart +.LmultiHartInit: # set MSIE bit to receive IPI li a2, MIP_MSIP csrw mie, a2 |