index
:
rocket-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
Unnamed repository; edit this file 'description' to name the repository.
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tree
commit
diff
log msg
author
committer
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Branch
Commit message
Author
Age
confprec
Remove debug printf in vsetprec
Quan Nguyen
11 years
cs250
don't forget to commit configure after autoconf!
Andrew Waterman
13 years
cycleh
Implement cycleh/instreth CSRs for RV32
Andrew Waterman
7 years
debug_rom
Clean up/optimize Debug ROM.
Tim Newsome
5 years
debug_rom_fence
Move fence inside entry_loop.
Tim Newsome
2 years
device_flags
Allow device flags after --device cmdline arg
Jerry Zhao
9 months
dtm_reset_error
Reset to "success" instead of "error."
Tim Newsome
7 years
dts_parsing
Support parsing procs fully from DTS
Jerry Zhao
7 weeks
dynamic
build: Dynamically link installed progs
Jerry Zhao
13 months
eos18-bringup
fix gcc 4.8 build
Yunsup Lee
11 years
factor-out-macros
Factor out P extension macros into their own header
Andrew Waterman
2 years
fix-bf16
Add f64_to_bf16; fix f32_to_bf16
Andrew Waterman
16 months
force-rtti
build: Include all symbols from extension.o when linking spike's main
Jerry Zhao
13 months
fp-encoding
WIP on FP encoding
Andrew Waterman
7 years
heterogeneous_mc
test_hetero_mc
Udit Khanna
4 years
hwachav4
Merge pull request #11 from arunthomas/readme
Andrew Waterman
10 years
increase-stack-size
Substantially increase context_t stack size
Andrew Waterman
24 months
itrigger-etrigger-cleanup
Use ACTION_DEBUG_MODE instead of 1
YenHaoChen
21 months
load_reservation_set_size
add configurable LR/SC reservation set
Udit Khanna
4 years
log-commits-faster
tmp
Andrew Waterman
9 months
master
Merge pull request #1722 from ved-rivos/smdbltrp
Andrew Waterman
7 hours
mmio-hack
Only allow SIP.SSIP to be toggled if the interrupt is delegated
Andrew Waterman
8 years
mvp
Add vf[ls](|seg)(|st)h and friends
Quan Nguyen
10 years
no_progbuf
Passes smoke tests with --progsize=0
Tim Newsome
7 years
no_progbuf2
Passes smoke tests with --progsize=0
Tim Newsome
7 years
nolibfdt
Remove in-tree libfdt, rely on system-installed libfdt
Jerry Zhao
8 months
p-ext-0.5.2
Merge pull request #694 from marcfedorow/p-ext
ChunPing Chung
3 years
plctlab-plct-zce-fix2
Contain C/Zc*-enable logic entirely within misa_csr_t
Andrew Waterman
18 months
plic-clint-endian
Make clint tolerant of discontiguous hart IDs
Andrew Waterman
18 months
plic_uart_v1
Merge branch 'master' into plic_uart_v1
Andrew Waterman
22 months
priv-1.10
minNum -> minimumNumber
Andrew Waterman
7 years
private-l1-caches
Make L1 cache models private caches
Andrew Waterman
4 years
pte-info-and-delegation
Allow delegating misaligned load/store, illegal instruction
Udit Khanna
5 years
remove-tests
Remove generic debug tests.
Tim Newsome
8 years
rivosinc-etrigger_fix_exception_match
Call stash_privilege more selectively
Andrew Waterman
15 months
rva-profile-support
WIP
Andrew Waterman
17 months
sifive/rvv0.9-phase2
rvv: index register doesn't care about NF
Chih-Min Chao
4 years
simplify-misaligned
Actually inline load_fast/store_fast for clang/ARM
Andrew Waterman
2 years
sodor
fesvr: decrease DTM idle cycles
kritik bhimani
5 years
sparse-mem
Add int_map and use it to speed up sparse mem
Andrew Waterman
4 years
speedup-hacks
tmp
Andrew Waterman
19 months
static-link
Add fesvr; only globally install fesvr headers/libs
Andrew Waterman
5 years
test
Enable precompiled headers when using clang
Andrew Waterman
3 years
tmp
For NS16550 UART, poll stdin less often
Andrew Waterman
19 months
trigger_priority
Simplify misaligned_load()
Tim Newsome
2 years
tweak_debug_rom
Debug ROM: Adjust debug ROM to have fewer icache flushes
Megan Wachs
6 years
whole-archive
build: Link spike binaries with --whole-archive
Jerry Zhao
13 months
Tag
Download
Author
Age
dummy-tag-for-ci-storage
riscv-isa-sim-dummy-tag-for-ci-storage.zip
riscv-isa-sim-dummy-tag-for-ci-storage.tar.gz
riscv-isa-sim-dummy-tag-for-ci-storage.tar.bz2
Andrew Waterman
23 months
v1.1.0
riscv-isa-sim-1.1.0.zip
riscv-isa-sim-1.1.0.tar.gz
riscv-isa-sim-1.1.0.tar.bz2
Andrew Waterman
3 years
v1.0.0
riscv-isa-sim-1.0.0.zip
riscv-isa-sim-1.0.0.tar.gz
riscv-isa-sim-1.0.0.tar.bz2
Andrew Waterman
5 years