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authorUdit Khanna <udit.khanna@sifive.com>2020-07-31 06:50:44 -0700
committerUdit Khanna <udit.khanna@sifive.com>2020-07-31 06:50:44 -0700
commit7b9f7c554911bdbb5e29ca4e2fcb6e88c3836198 (patch)
tree9a3e9776289ba9841f13f39f557e883be885eb24
parent6859ccfa4a20295810dfe9d92582504b8ce23643 (diff)
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test_hetero_mcheterogeneous_mc
-rw-r--r--riscv/sim.cc4
1 files changed, 3 insertions, 1 deletions
diff --git a/riscv/sim.cc b/riscv/sim.cc
index 2aced1b..460897a 100644
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -75,9 +75,11 @@ sim_t::sim_t(const char* isa, const char* priv, const char* varch,
exit(1);
}
+ const char* hart_isa[5] = {"rv64imac", "rv64imafdc", "rv64imafdc", "rv64imafdc", "rv64imafdc"};
+ const char* hart_priv[5] = {"m", "mu", "msu", "msu", "msu"};
for (size_t i = 0; i < nprocs; i++) {
int hart_id = hartids.empty() ? i : hartids[i];
- procs[i] = new processor_t(isa, priv, varch, this, hart_id, halted,
+ procs[i] = new processor_t(hart_isa[hart_id], hart_priv[hart_id], varch, this, hart_id, halted,
log_file.get());
}