rocket-tools/riscv-isa-sim.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2017-04-10	WIP on FP encodingfp-encoding	Andrew Waterman	19	-34/+31
2017-04-09	WIP on FP encoding	Andrew Waterman	50	-63/+89
2017-04-07	Implement vectored interrupt proposal	Andrew Waterman	1	-3/+5
2017-04-05	Add --enable-misaligned option for misaligned ld/st support	Andrew Waterman	4	-4/+50
2017-03-31	update encoding.h to get PMP updates	Yunsup Lee	1	-5/+6
2017-03-31	Update LICENSE copyright date	Andrew Waterman	1	-2/+2
2017-03-30	fdt: move interrupt controller into its own node	Wesley W. Terpstra	1	-4/+7
2017-03-27	Set badaddr=0 on illegal instruction traps	Andrew Waterman	4	-7/+7
2017-03-27	On EBREAK, set badaddr to pc	Andrew Waterman	3	-3/+3
2017-03-27	Separate page faults from physical memory access exceptions	Andrew Waterman	4	-13/+25
2017-03-24	Default to 2 GiB of memory	Andrew Waterman	1	-1/+1
2017-03-23	Require little-endian host	Andrew Waterman	2	-0/+14
2017-03-22	riscv: replace rtc device with a real clint implementation	Wesley W. Terpstra	8	-55/+96
2017-03-21	sim: declare cores as interrupt-controllers for clint	Wesley W. Terpstra	1	-0/+2
2017-03-21	bootrom: set a0 to hartid and a1 to dtb before boot	Wesley W. Terpstra	1	-7/+7
2017-03-21	configstring: rename variables to dts	Wesley W. Terpstra	3	-12/+12
2017-03-21	riscv: remove dependency on num_cores	Wesley W. Terpstra	3	-5/+1
2017-03-21	bootrom: include compiled dtb	Wesley W. Terpstra	1	-1/+87
2017-03-21	sim: create DTS instead of config string	Wesley W. Terpstra	1	-26/+45
2017-03-21	sim: define emulated CPU clock rate to be 1GHz	Wesley W. Terpstra	1	-0/+1
2017-03-21	autoconf: put location of 'dtc' into config.h	Wesley W. Terpstra	4	-0/+52
2017-03-20	PUM -> SUM; expose MXR to S-mode	Andrew Waterman	3	-8/+9
2017-03-16	Simplify interrupt-stack discipline	Andrew Waterman	4	-4/+44
2017-03-13	Implement mstatus.TW, mstatus.TVM, and mstatus.TSR	Andrew Waterman	5	-4/+12
2017-03-07	Don't overload illegal instruction trap in interactive code	Andrew Waterman	1	-8/+10
2017-02-26	Sv57 and Sv64 are not spec'd yet	Andrew Waterman	2	-15/+11
2017-02-25	New counter enable scheme	Andrew Waterman	3	-31/+22
2017-02-20	serialize simulator on wfi	Andrew Waterman	3	-4/+5
2017-02-20	Take M-mode interrupts over S-mode interrupts	Andrew Waterman	1	-1/+2
2017-02-20	permit MMIO loads to MSIP bit	Andrew Waterman	1	-7/+18
2017-02-18	Make HW setting of PTE A/D bits optional (by configure arg)	Andrew Waterman	4	-2/+45
2017-02-18	Spike uarch needs TLB flush after SPTBR write	Andrew Waterman	2	-1/+1
2017-02-15	sfence.vm -> sfence.vma	Andrew Waterman	3	-4/+4
2017-02-08	Encode VM type in sptbr, not mstatus	Andrew Waterman	6	-137/+192
2017-02-07	Merge pull request #83 from bacam/gdb-protocol-fixes	Tim Newsome	1	-5/+7
2017-02-02	Fix interrupt delegation for coprocessors	Andrew Waterman	4	-19/+6
2017-02-01	For FMIN(sNaN, x) and FMIN(qNaN, qNaN), return canonical NaN	Andrew Waterman	5	-4/+13
2017-02-01	Set xPIE=1 on xRET	Andrew Waterman	2	-2/+2
2017-01-07	Only allow SIP.SSIP to be toggled if the interrupt is delegated	Andrew Waterman	1	-1/+1
2017-01-07	Make SIP.STIP read-only	Andrew Waterman	1	-3/+4
2017-01-06	Comply with GNU coding standards.	David Craven	1	-2/+2
2016-12-30	Only read exception flag in gdb register read/write. (#85)	Brian Campbell	1	-2/+2
2016-12-21	Fix gdb communication error (#82)	Brian Campbell	1	-1/+1
2016-12-21	Remove extra gdb protocol responses on register writes	Brian Campbell	1	-2/+0
2016-12-21	Fix gdb protocol register read of S0	Brian Campbell	1	-3/+7
2016-12-16	Use correct format codes for reg_t and size_t	Stefan O'Rear	3	-14/+15
2016-12-15	Fix single stepping over faulting instructions. (#80)	Tim Newsome	1	-0/+5
2016-12-12	Reuse the ebreak constants in encoding.h.	Tim Newsome	1	-9/+7
2016-12-01	Added comments about the modified Duff's Device in execute.cc (#77)	Andy Wright	1	-0/+37
2016-11-13	Fix 32-bit host portability bug	Andrew Waterman	1	-1/+1