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| author | Udit Khanna <udit.khanna@sifive.com> | 2019-11-21 18:16:45 -0800 |
|---|---|---|
| committer | Udit Khanna <udit.khanna@sifive.com> | 2019-11-21 18:16:45 -0800 |
| commit | 1536d43028fb466a4346ec9b794e584d99dbeefd (patch) | |
| tree | 262f47664a20904f63af3adaa2512e381fccfff7 | |
| parent | e535f16fc5f9f8d0801243080da8471d29414d1a (diff) | |
| download | riscv-isa-sim-pte-info-and-delegation.zip riscv-isa-sim-pte-info-and-delegation.tar.gz riscv-isa-sim-pte-info-and-delegation.tar.bz2 | |
Allow delegating misaligned load/store, illegal instructionpte-info-and-delegation
| -rw-r--r-- | riscv/processor.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/processor.cc b/riscv/processor.cc index 5f956a1..ad100e6 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -537,6 +537,9 @@ void processor_t::set_csr(int which, reg_t val) (1 << CAUSE_USER_ECALL) | (1 << CAUSE_FETCH_PAGE_FAULT) | (1 << CAUSE_LOAD_PAGE_FAULT) | + (1 << CAUSE_MISALIGNED_LOAD) | + (1 << CAUSE_MISALIGNED_STORE) | + (1 << CAUSE_ILLEGAL_INSTRUCTION) | (1 << CAUSE_STORE_PAGE_FAULT); state.medeleg = (state.medeleg & ~mask) | (val & mask); break; |