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AgeCommit message (Expand)AuthorFilesLines
12 hourspointer masking: refactor: Use xlen to avoid sketchy, hardcoded number 64YenHaoChen1-1/+2
2 dayspointer masking: Fix: Let transformed_addr of fetching be unchangedYenHaoChen1-4/+5
14 daysLet MXR not affect implicit memory access for VS-stage address translationYenHaoChen1-1/+1
2024-07-06pointer masking: Implement hstatus.HUPMM (Flush TLB on changing hstatus.HUPMM)YenHaoChen1-0/+4
2024-07-06pointer masking: Implement [sh]envcfg.PMMYenHaoChen1-0/+4
2024-07-06pointer masking: Implement Smnpm (Flush TLB on changing *envcfg.PMM)YenHaoChen1-0/+2
2024-07-06pointer masking: Let HLVX.* instructions not subject to pointer maskingYenHaoChen1-3/+3
2024-07-06pointer masking: Let pointer masking not apply when both MPRV and MXR are setYenHaoChen1-1/+1
2024-07-06refactor: Rename parameter addr to original_addr in store_slow_path()YenHaoChen1-2/+2
2024-07-06pointer masking: performance: Move pointer masking out of store fast pathYenHaoChen1-9/+11
2024-07-06refactor: Rename parameter addr to original_addr in load_slow_path()YenHaoChen1-2/+2
2024-07-06pointer masking: performance: Move pointer masking out of load fast pathYenHaoChen1-13/+15
2024-07-06pointer masking: Let load take into account pointer maskingYenHaoChen1-2/+22
2024-07-06refactor: Move implementation of generate_access_info() to riscv/mmu.ccYenHaoChen1-0/+19
2024-07-16zicfiss: modify check condicton to loads to shadow-stack pagesBinno1-3/+4
2024-07-16zicfiss: fix missed throw to store access fault of shadow stack pageBinno1-1/+1
2024-07-01Loads to shadow-stack pages are allowedAndrew Waterman1-1/+1
2024-04-29add hlvx pmp protect to fix issue 1557xinyuwang-sifive1-3/+3
2024-04-18Add Zicfiss extension from CFI extension, v0.4.0SuHsien Ho1-3/+26
2024-01-24Use designated initiallizers to construct xlate_flags_t objectsrbuchner1-1/+1
2023-08-27report right pseudo-inst for guest PF caused for VS-stage addr transVed Shanbhogue1-8/+16
2023-08-27check g-stage write perm and set D bit in g-stage pte for vs-stage pte A/D up...Ved Shanbhogue1-0/+3
2023-08-14rename *envcfg.HADE to *envcfg.ADUEVed Shanbhogue1-2/+2
2023-07-13refactor: mcontrol/mcontrol6: extend check_triggers() with tval parameterYenHaoChen1-3/+3
2023-06-19mmu: support load/store longer than 64-bits.Gianluca Guida1-2/+15
2023-05-11Plumb in effective virtual bit to take_trigger_action()rbuchner1-8/+8
2023-05-11Add split_misaligned_access() to mem_access_info_trbuchner1-2/+2
2023-05-11Pass mem_access_info_t into walk()rbuchner1-3/+7
2023-05-11Use access_info within store_slow_path rather than xlate_flagsRyan Buchner1-1/+1
2023-05-11Use access_info.effective_virt when failed mmio_store (i.e. device detects ac...rbuchner1-1/+1
2023-05-11Adjust store_slow_path_intrapage to recieve a mem_access_info_t as inputRyan Buchner1-7/+9
2023-05-11Use access_info within load_slow_path rather than xlate_flagsRyan Buchner1-2/+2
2023-05-11Use access_info.effective_virt when failed mmio_load (i.e. device detects acc...rbuchner1-1/+1
2023-05-11Use access_info.effective_virt when access_fault due to non-reservable lrrbuchner1-1/+1
2023-05-11Adjust load_slow_path_intrapage to recieve a mem_access_info_t as inputRyan Buchner1-9/+11
2023-05-11Add structure (mem_access_info_t) for holding memory access informationRyan Buchner1-18/+10
2023-05-11Add is_special_access() to xlate_flags_trbuchner1-4/+4
2023-05-11Add xlate_flags_t structrbuchner1-17/+17
2023-05-11Rename RISCV_XLATE_VIRT to RISCV_XLATE_FORCED_VIRTRyan Buchner1-3/+3
2023-03-16Make MPRV logic consistent; factor it outAndrew Waterman1-2/+2
2023-03-04Don't issue misaligned or non-power-of-2 MMIO accessesScott Johnson1-7/+24
2023-01-27Use Svadu control bits to drive A/D updatesAaron Durbin1-2/+4
2023-01-04Respect --mmu-dirty flag instead of --enable-dirtyJerry Zhao1-16/+18
2023-01-03Respect --[no-]misaligned command-line flagAndrew Waterman1-8/+6
2023-01-03Merge pull request #1200 from riscv-software-src/mmio_pteAndrew Waterman1-18/+5
2023-01-03Pull pte load/store into methods of mmu_tJerry Zhao1-18/+5
2023-01-03Add method to probe which memory regions are reservableJerry Zhao1-4/+9
2023-01-03Specify addresses are physical for simif_t member functionsJerry Zhao1-11/+11
2022-12-23Add mmio_fetch to simif_t to distinguish between fetch/load for mmio accessesJerry Zhao1-1/+9
2022-12-15Add config.h includes directly to source files instead of relying on header c...Jerry Zhao1-0/+1
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