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author | Ryan Buchner <ryan.buchner@arilinc.com> | 2023-04-17 20:34:29 -0700 |
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committer | rbuchner <ryan.buchner@arilinc.com> | 2023-05-11 23:00:59 -0700 |
commit | f7900e4730e1c13fa42789bc01d8f0366756130e (patch) | |
tree | 769e0116dd1bd44d7153fefbb67d278a80c31817 /riscv/mmu.cc | |
parent | 850600792ec04756f7720a9b376cfb2d8ad6c917 (diff) | |
download | riscv-isa-sim-f7900e4730e1c13fa42789bc01d8f0366756130e.zip riscv-isa-sim-f7900e4730e1c13fa42789bc01d8f0366756130e.tar.gz riscv-isa-sim-f7900e4730e1c13fa42789bc01d8f0366756130e.tar.bz2 |
Use access_info within store_slow_path rather than xlate_flags
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r-- | riscv/mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index a524035..7264ea8 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -280,7 +280,7 @@ void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, xlate_f check_triggers(triggers::OPERATION_STORE, addr, reg_from_bytes(len, bytes)); if (addr & (len - 1)) { - bool gva = ((proc) ? proc->state.v : false) || xlate_flags.forced_virt; + bool gva = access_info.effective_virt; if (!is_misaligned_enabled()) throw trap_store_address_misaligned(gva, addr, 0, 0); |