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authorRyan Buchner <ryan.buchner@arilinc.com>2023-04-17 18:53:27 -0700
committerrbuchner <ryan.buchner@arilinc.com>2023-05-11 23:00:58 -0700
commit3286d262eb42f414e7e43c734532f309dee9fe81 (patch)
tree6d5dc02a01d222e803a733de32a622c855ccdfcb /riscv/mmu.cc
parentdc3eb2d9e3b805ed1a1416c1e66584cf6520d0f1 (diff)
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Rename RISCV_XLATE_VIRT to RISCV_XLATE_FORCED_VIRT
More readable/understandable.
Diffstat (limited to 'riscv/mmu.cc')
-rw-r--r--riscv/mmu.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index be24f40..f6f0a0d 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -66,7 +66,7 @@ reg_t mmu_t::translate(reg_t addr, reg_t len, access_type type, uint32_t xlate_f
if (get_field(proc->state.mstatus->read(), MSTATUS_MPV) && mode != PRV_M)
virt = true;
}
- if (xlate_flags & RISCV_XLATE_VIRT) {
+ if (xlate_flags & RISCV_XLATE_FORCED_VIRT) {
virt = true;
mode = get_field(proc->state.hstatus->read(), HSTATUS_SPVP);
}
@@ -236,7 +236,7 @@ void mmu_t::load_slow_path(reg_t addr, reg_t len, uint8_t* bytes, uint32_t xlate
if ((addr & (len - 1)) == 0) {
load_slow_path_intrapage(addr, len, bytes, xlate_flags);
} else {
- bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags);
+ bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_FORCED_VIRT & xlate_flags);
if (!is_misaligned_enabled())
throw trap_load_address_misaligned(gva, addr, 0, 0);
@@ -284,7 +284,7 @@ void mmu_t::store_slow_path(reg_t addr, reg_t len, const uint8_t* bytes, uint32_
check_triggers(triggers::OPERATION_STORE, addr, reg_from_bytes(len, bytes));
if (addr & (len - 1)) {
- bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_VIRT & xlate_flags);
+ bool gva = ((proc) ? proc->state.v : false) || (RISCV_XLATE_FORCED_VIRT & xlate_flags);
if (!is_misaligned_enabled())
throw trap_store_address_misaligned(gva, addr, 0, 0);