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| author | Ved Shanbhogue <ved@rivosinc.com> | 2023-08-27 14:13:13 -0500 |
|---|---|---|
| committer | Ved Shanbhogue <ved@rivosinc.com> | 2023-08-27 14:13:13 -0500 |
| commit | ae9888e50806837a3b6a39293c1014d9c7c37c56 (patch) | |
| tree | 4e0469736416c30d59f4ca4b1674f57942cc1621 /riscv/mmu.cc | |
| parent | 5854ab52181f96723178f903e623d21e61f4fe61 (diff) | |
| download | riscv-isa-sim-ae9888e50806837a3b6a39293c1014d9c7c37c56.zip riscv-isa-sim-ae9888e50806837a3b6a39293c1014d9c7c37c56.tar.gz riscv-isa-sim-ae9888e50806837a3b6a39293c1014d9c7c37c56.tar.bz2 | |
check g-stage write perm and set D bit in g-stage pte for vs-stage pte A/D updates
Diffstat (limited to 'riscv/mmu.cc')
| -rw-r--r-- | riscv/mmu.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/mmu.cc b/riscv/mmu.cc index 285ef6d..1473e89 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -536,6 +536,9 @@ reg_t mmu_t::walk(mem_access_info_t access_info) if ((pte & ad) != ad) { if (hade) { + // Check for write permission to the first-stage PT in second-stage + // PTE and set the D bit in the second-stage PTE if needed + s2xlate(addr, base + idx * vm.ptesize, STORE, type, virt, false); // set accessed and possibly dirty bits. pte_store(pte_paddr, pte | ad, addr, virt, type, vm.ptesize); } else { |