| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2024-06-11 | Separate RV32 and RV64 C instructions into separate files | Andrew Waterman | 1 | -8/+3 |
| 2022-11-17 | add support for zca zcd and zcf | Weiwei Li | 1 | -2/+2 |
| 2022-10-19 | Template-ize stores | Andrew Waterman | 1 | -2/+2 |
| 2017-09-28 | Implement Q extension | Andrew Waterman | 1 | -1/+1 |
| 2017-04-10 | Implement new FP encoding | Andrew Waterman | 1 | -1/+1 |
| 2015-10-02 | work towards rvc 1.8 | Andrew Waterman | 1 | -1/+1 |
| 2015-09-04 | Move towards RVC v1.8 | Andrew Waterman | 1 | -0/+8 |
| 2013-07-26 | Rip out RVC for now | Andrew Waterman | 1 | -3/+0 |
| 2011-06-19 | temporary undoing of renaming | Andrew Waterman | 1 | -0/+3 |
| 2011-06-12 | [sim] renamed to riscv-isa-run | Andrew Waterman | 1 | -3/+0 |
| 2011-04-24 | [xcc,sim,opcodes] added more RVC instructions | Andrew Waterman | 1 | -0/+3 |
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index : rocket-tools/riscv-isa-sim.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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