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| author | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:40:42 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-10-19 21:40:42 -0700 |
| commit | b1f2ae41a1e64f416fb5f5aa092352439ecefa83 (patch) | |
| tree | a5918c9e5ff22fb72c568f9751602ebbd8974d0f /riscv/insns/c_fsw.h | |
| parent | d41af9f81cb393ed6fad8b9cb756a5b459e7c9ab (diff) | |
| download | riscv-isa-sim-b1f2ae41a1e64f416fb5f5aa092352439ecefa83.zip riscv-isa-sim-b1f2ae41a1e64f416fb5f5aa092352439ecefa83.tar.gz riscv-isa-sim-b1f2ae41a1e64f416fb5f5aa092352439ecefa83.tar.bz2 | |
Template-ize stores
Diffstat (limited to 'riscv/insns/c_fsw.h')
| -rw-r--r-- | riscv/insns/c_fsw.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h index 7085822..381ab5e 100644 --- a/riscv/insns/c_fsw.h +++ b/riscv/insns/c_fsw.h @@ -2,7 +2,7 @@ require_extension('C'); if (xlen == 32) { require_extension('F'); require_fp; - MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]); + MMU.store<uint32_t>(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]); } else { // c.sd - MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S); + MMU.store<uint64_t>(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S); } |