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| author | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-06-19 20:47:29 -0700 |
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| committer | Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU> | 2011-06-19 20:47:29 -0700 |
| commit | 77452a26e7d95d29dbaa797595ae683f03a3345b (patch) | |
| tree | e7aaae682f73a20ceb4d3366528b0cd38378f49d /riscv/insns/c_fsw.h | |
| parent | 740f981cfd55604d46598144dccac26dd53f643c (diff) | |
| download | riscv-isa-sim-77452a26e7d95d29dbaa797595ae683f03a3345b.zip riscv-isa-sim-77452a26e7d95d29dbaa797595ae683f03a3345b.tar.gz riscv-isa-sim-77452a26e7d95d29dbaa797595ae683f03a3345b.tar.bz2 | |
temporary undoing of renaming
Diffstat (limited to 'riscv/insns/c_fsw.h')
| -rw-r--r-- | riscv/insns/c_fsw.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h new file mode 100644 index 0000000..1d21629 --- /dev/null +++ b/riscv/insns/c_fsw.h @@ -0,0 +1,3 @@ +require_rvc; +require_fp; +mmu.store_uint32(CRS1S+CIMM5*4, FCRS2S); |