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| author | Andrew Waterman <andrew@sifive.com> | 2017-09-24 20:34:04 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-09-28 15:56:47 -0700 |
| commit | 85c40db208db3e26f507dc6a74a5dc540b504b5c (patch) | |
| tree | 88ddd7440be666a4305a55e4ca1130ae7636a4f6 /riscv/insns/c_fsw.h | |
| parent | bd85811c35ea38180d27440507fc222d585ef780 (diff) | |
| download | riscv-isa-sim-85c40db208db3e26f507dc6a74a5dc540b504b5c.zip riscv-isa-sim-85c40db208db3e26f507dc6a74a5dc540b504b5c.tar.gz riscv-isa-sim-85c40db208db3e26f507dc6a74a5dc540b504b5c.tar.bz2 | |
Implement Q extension
Diffstat (limited to 'riscv/insns/c_fsw.h')
| -rw-r--r-- | riscv/insns/c_fsw.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h index b924a46..7085822 100644 --- a/riscv/insns/c_fsw.h +++ b/riscv/insns/c_fsw.h @@ -2,7 +2,7 @@ require_extension('C'); if (xlen == 32) { require_extension('F'); require_fp; - MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v); + MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v[0]); } else { // c.sd MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S); } |