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| author | Andrew Waterman <andrew@sifive.com> | 2017-04-10 17:35:24 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-04-10 17:35:24 -0700 |
| commit | d6fce459767509249311a120fddb21c844dc9b2c (patch) | |
| tree | b54272d8ce52f773b13dd33ae94d634538ec6599 /riscv/insns/c_fsw.h | |
| parent | 5f494a22db29d69893db4b39f488cf67c0ac6437 (diff) | |
| download | riscv-isa-sim-d6fce459767509249311a120fddb21c844dc9b2c.zip riscv-isa-sim-d6fce459767509249311a120fddb21c844dc9b2c.tar.gz riscv-isa-sim-d6fce459767509249311a120fddb21c844dc9b2c.tar.bz2 | |
Implement new FP encoding
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/_r7hBlzsEd8/cWPyJKMzCQAJ
Diffstat (limited to 'riscv/insns/c_fsw.h')
| -rw-r--r-- | riscv/insns/c_fsw.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/riscv/insns/c_fsw.h b/riscv/insns/c_fsw.h index 8923fef..b924a46 100644 --- a/riscv/insns/c_fsw.h +++ b/riscv/insns/c_fsw.h @@ -2,7 +2,7 @@ require_extension('C'); if (xlen == 32) { require_extension('F'); require_fp; - MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S); + MMU.store_uint32(RVC_RS1S + insn.rvc_lw_imm(), RVC_FRS2S.v); } else { // c.sd MMU.store_uint64(RVC_RS1S + insn.rvc_ld_imm(), RVC_RS2S); } |