diff options
Diffstat (limited to 'riscv')
145 files changed, 245 insertions, 243 deletions
diff --git a/riscv/decode.h b/riscv/decode.h index 627502e..f99e9eb 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -78,10 +78,10 @@ const int JUMP_ALIGN_BITS = 1; // note: bit fields are in little-endian order struct itype_t { - unsigned imm : IMM_BITS; + unsigned imm12 : IMM_BITS; unsigned funct : FUNCT_BITS; - unsigned rb : GPRID_BITS; - unsigned ra : GPRID_BITS; + unsigned rs1 : GPRID_BITS; + unsigned rdi : GPRID_BITS; unsigned opcode : OPCODE_BITS; }; @@ -93,28 +93,28 @@ struct jtype_t struct rtype_t { - unsigned rc : GPRID_BITS; + unsigned rdr : GPRID_BITS; unsigned functr : FUNCTR_BITS; unsigned funct : FUNCT_BITS; - unsigned rb : GPRID_BITS; - unsigned ra : GPRID_BITS; + unsigned rs1 : GPRID_BITS; + unsigned rs2 : GPRID_BITS; unsigned opcode : OPCODE_BITS; }; struct btype_t { unsigned bigimm : BIGIMM_BITS; - unsigned rt : GPRID_BITS; + unsigned rdi : GPRID_BITS; unsigned opcode : OPCODE_BITS; }; struct ftype_t { - unsigned rc : FPRID_BITS; - unsigned rd : FPRID_BITS; + unsigned rdr : FPRID_BITS; + unsigned rs3 : FPRID_BITS; unsigned ffunct : FFUNCT_BITS; - unsigned rb : FPRID_BITS; - unsigned ra : FPRID_BITS; + unsigned rs1 : FPRID_BITS; + unsigned rs2 : FPRID_BITS; unsigned opcode : OPCODE_BITS; }; @@ -129,18 +129,20 @@ union insn_t }; // helpful macros, etc -#define RA R[insn.rtype.ra] -#define RB R[insn.rtype.rb] -#define RC R[insn.rtype.rc] -#define FRA FR[insn.ftype.ra] -#define FRB FR[insn.ftype.rb] -#define FRC FR[insn.ftype.rc] -#define FRD FR[insn.ftype.rd] +#define RS1 R[insn.rtype.rs1] +#define RS2 R[insn.rtype.rs2] +#define RDR R[insn.rtype.rdr] +#define RDI R[insn.itype.rdi] +#define FRS1 FR[insn.ftype.rs1] +#define FRS2 FR[insn.ftype.rs2] +#define FRS3 FR[insn.ftype.rs3] +#define FRDR FR[insn.ftype.rdr] +#define FRDI FR[insn.itype.rdi] #define BIGIMM insn.btype.bigimm -#define IMM insn.itype.imm -#define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS)) -#define SHAMT (insn.itype.imm & 0x3F) -#define SHAMTW (insn.itype.imm & 0x1F) +#define IMM insn.itype.imm12 +#define SIMM ((int32_t)((uint32_t)insn.itype.imm12<<(32-IMM_BITS))>>(32-IMM_BITS)) +#define SHAMT (insn.itype.imm12 & 0x3F) +#define SHAMTW (insn.itype.imm12 & 0x1F) #define TARGET insn.jtype.target #define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS)) #define JUMP_TARGET ((npc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS)) diff --git a/riscv/execute.h b/riscv/execute.h index 349fa9e..2c500c4 100644 --- a/riscv/execute.h +++ b/riscv/execute.h @@ -77,12 +77,12 @@ switch((insn.bits >> 0x19) & 0x7f) #include "insns/sgninj_s.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd00004c0) + if((insn.bits & 0xfff07fe0) == 0xd00004c0) { #include "insns/cvt_s_w.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0000440) + if((insn.bits & 0xfff07fe0) == 0xd0000440) { #include "insns/trunc_w_s.h" break; @@ -97,22 +97,22 @@ switch((insn.bits >> 0x19) & 0x7f) #include "insns/sgninjn_s.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0000400) + if((insn.bits & 0xfff07fe0) == 0xd0000400) { #include "insns/trunc_l_s.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd00004e0) + if((insn.bits & 0xfff07fe0) == 0xd00004e0) { #include "insns/cvtu_s_w.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0000420) + if((insn.bits & 0xfff07fe0) == 0xd0000420) { #include "insns/truncu_l_s.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd00004a0) + if((insn.bits & 0xfff07fe0) == 0xd00004a0) { #include "insns/cvtu_s_l.h" break; @@ -122,7 +122,7 @@ switch((insn.bits >> 0x19) & 0x7f) #include "insns/sub_s.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0000080) + if((insn.bits & 0xfff07fe0) == 0xd0000080) { #include "insns/sqrt_s.h" break; @@ -137,7 +137,7 @@ switch((insn.bits >> 0x19) & 0x7f) #include "insns/sgnmul_s.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0000480) + if((insn.bits & 0xfff07fe0) == 0xd0000480) { #include "insns/cvt_s_l.h" break; @@ -147,7 +147,7 @@ switch((insn.bits >> 0x19) & 0x7f) #include "insns/div_s.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0000660) + if((insn.bits & 0xfff07fe0) == 0xd0000660) { #include "insns/cvt_s_d.h" break; @@ -162,7 +162,7 @@ switch((insn.bits >> 0x19) & 0x7f) #include "insns/mul_s.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0000460) + if((insn.bits & 0xfff07fe0) == 0xd0000460) { #include "insns/truncu_w_s.h" break; @@ -186,17 +186,17 @@ switch((insn.bits >> 0x19) & 0x7f) #include "insns/c_eq_d.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd00064a0) + if((insn.bits & 0xfff07fe0) == 0xd00064a0) { #include "insns/cvtu_d_l.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0006440) + if((insn.bits & 0xfff07fe0) == 0xd0006440) { #include "insns/trunc_w_d.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd00064e0) + if((insn.bits & 0xfff07fe0) == 0xd00064e0) { #include "insns/cvtu_d_w.h" break; @@ -221,17 +221,17 @@ switch((insn.bits >> 0x19) & 0x7f) #include "insns/sgninjn_d.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0006600) + if((insn.bits & 0xfff07fe0) == 0xd0006600) { #include "insns/cvt_d_s.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0006400) + if((insn.bits & 0xfff07fe0) == 0xd0006400) { #include "insns/trunc_l_d.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0006420) + if((insn.bits & 0xfff07fe0) == 0xd0006420) { #include "insns/truncu_l_d.h" break; @@ -241,22 +241,22 @@ switch((insn.bits >> 0x19) & 0x7f) #include "insns/sub_d.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0006080) + if((insn.bits & 0xfff07fe0) == 0xd0006080) { #include "insns/sqrt_d.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd00064c0) + if((insn.bits & 0xfff07fe0) == 0xd00064c0) { #include "insns/cvt_d_w.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0006480) + if((insn.bits & 0xfff07fe0) == 0xd0006480) { #include "insns/cvt_d_l.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd0006460) + if((insn.bits & 0xfff07fe0) == 0xd0006460) { #include "insns/truncu_w_d.h" break; @@ -317,12 +317,12 @@ switch((insn.bits >> 0x19) & 0x7f) { case 0x0: { - if((insn.bits & 0xfe0fffe0) == 0xd4000000) + if((insn.bits & 0xfff07fe0) == 0xd4000000) { #include "insns/mff_s.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd4000800) + if((insn.bits & 0xfff07fe0) == 0xd4000800) { #include "insns/mtf_s.h" break; @@ -331,12 +331,12 @@ switch((insn.bits >> 0x19) & 0x7f) } case 0x6: { - if((insn.bits & 0xfe0fffe0) == 0xd4006000) + if((insn.bits & 0xfff07fe0) == 0xd4006000) { #include "insns/mff_d.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd4006400) + if((insn.bits & 0xfff07fe0) == 0xd4006400) { #include "insns/mffh_d.h" break; @@ -346,7 +346,7 @@ switch((insn.bits >> 0x19) & 0x7f) #include "insns/mtflh_d.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xd4006800) + if((insn.bits & 0xfff07fe0) == 0xd4006800) { #include "insns/mtf_d.h" break; @@ -947,17 +947,17 @@ switch((insn.bits >> 0x19) & 0x7f) { case 0x0: { - if((insn.bits & 0xfe0fffe0) == 0xf6000000) + if((insn.bits & 0xfff07fe0) == 0xf6000000) { #include "insns/jalr_c.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xf6000040) + if((insn.bits & 0xfff07fe0) == 0xf6000040) { #include "insns/jalr_j.h" break; } - if((insn.bits & 0xfe0fffe0) == 0xf6000020) + if((insn.bits & 0xfff07fe0) == 0xf6000020) { #include "insns/jalr_r.h" break; @@ -975,7 +975,7 @@ switch((insn.bits >> 0x19) & 0x7f) } case 0x2: { - if((insn.bits & 0xfff07fe0) == 0xf6002000) + if((insn.bits & 0xfe0fffe0) == 0xf6002000) { #include "insns/mfcr.h" break; @@ -1058,7 +1058,7 @@ switch((insn.bits >> 0x19) & 0x7f) } case 0x4: { - if((insn.bits & 0xfff07fe0) == 0xfc004000) + if((insn.bits & 0xfe0fffe0) == 0xfc004000) { #include "insns/mfpcr.h" break; diff --git a/riscv/insns/add.h b/riscv/insns/add.h index 746cd80..f7dede9 100644 --- a/riscv/insns/add.h +++ b/riscv/insns/add.h @@ -1,2 +1,2 @@ require64; -RC = RA + RB; +RDR = RS1 + RS2; diff --git a/riscv/insns/add_d.h b/riscv/insns/add_d.h index 964aa20..eae2c6e 100644 --- a/riscv/insns/add_d.h +++ b/riscv/insns/add_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_add(FRA, FRB); +FRDR = f64_add(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/add_s.h b/riscv/insns/add_s.h index d4d0cd6..7c9dc50 100644 --- a/riscv/insns/add_s.h +++ b/riscv/insns/add_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_add(FRA, FRB); +FRDR = f32_add(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/addi.h b/riscv/insns/addi.h index b6b208d..e813eae 100644 --- a/riscv/insns/addi.h +++ b/riscv/insns/addi.h @@ -1,2 +1,2 @@ require64; -RA = SIMM + RB; +RDI = SIMM + RS1; diff --git a/riscv/insns/addiw.h b/riscv/insns/addiw.h index 6935cca..6dfe5b1 100644 --- a/riscv/insns/addiw.h +++ b/riscv/insns/addiw.h @@ -1 +1 @@ -RA = sext32(SIMM + RB); +RDI = sext32(SIMM + RS1); diff --git a/riscv/insns/addw.h b/riscv/insns/addw.h index bfbc485..d95c95f 100644 --- a/riscv/insns/addw.h +++ b/riscv/insns/addw.h @@ -1,2 +1,2 @@ -RC = sext32(RA + RB); +RDR = sext32(RS1 + RS2); diff --git a/riscv/insns/amo_add.h b/riscv/insns/amo_add.h index 0ea6782..18f6f4e 100644 --- a/riscv/insns/amo_add.h +++ b/riscv/insns/amo_add.h @@ -1,4 +1,4 @@ require64; -reg_t v = mmu.load_uint64(RB); -mmu.store_uint64(RB, RA + v); -RC = v; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, RS2 + v); +RDR = v; diff --git a/riscv/insns/amo_and.h b/riscv/insns/amo_and.h index c86e537..dd187df 100644 --- a/riscv/insns/amo_and.h +++ b/riscv/insns/amo_and.h @@ -1,4 +1,4 @@ require64; -reg_t v = mmu.load_uint64(RB); -mmu.store_uint64(RB, RA & v); -RC = v; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, RS2 & v); +RDR = v; diff --git a/riscv/insns/amo_max.h b/riscv/insns/amo_max.h index 6e3eeb6..296b86a 100644 --- a/riscv/insns/amo_max.h +++ b/riscv/insns/amo_max.h @@ -1,4 +1,4 @@ require64; -sreg_t v = mmu.load_int64(RB); -mmu.store_uint64(RB, std::max(sreg_t(RA),v)); -RC = v; +sreg_t v = mmu.load_int64(RS1); +mmu.store_uint64(RS1, std::max(sreg_t(RS2),v)); +RDR = v; diff --git a/riscv/insns/amo_maxu.h b/riscv/insns/amo_maxu.h index 471a119..533dde3 100644 --- a/riscv/insns/amo_maxu.h +++ b/riscv/insns/amo_maxu.h @@ -1,4 +1,4 @@ require64; -reg_t v = mmu.load_uint64(RB); -mmu.store_uint64(RB, std::max(RA,v)); -RC = v; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, std::max(RS2,v)); +RDR = v; diff --git a/riscv/insns/amo_min.h b/riscv/insns/amo_min.h index 8235504..7244e87 100644 --- a/riscv/insns/amo_min.h +++ b/riscv/insns/amo_min.h @@ -1,4 +1,4 @@ require64; -sreg_t v = mmu.load_int64(RB); -mmu.store_uint64(RB, std::min(sreg_t(RA),v)); -RC = v; +sreg_t v = mmu.load_int64(RS1); +mmu.store_uint64(RS1, std::min(sreg_t(RS2),v)); +RDR = v; diff --git a/riscv/insns/amo_minu.h b/riscv/insns/amo_minu.h index 0b617a1..3e365ab 100644 --- a/riscv/insns/amo_minu.h +++ b/riscv/insns/amo_minu.h @@ -1,4 +1,4 @@ require64; -reg_t v = mmu.load_uint64(RB); -mmu.store_uint64(RB, std::min(RA,v)); -RC = v; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, std::min(RS2,v)); +RDR = v; diff --git a/riscv/insns/amo_or.h b/riscv/insns/amo_or.h index 790a98c..e7d81a8 100644 --- a/riscv/insns/amo_or.h +++ b/riscv/insns/amo_or.h @@ -1,4 +1,4 @@ require64; -reg_t v = mmu.load_uint64(RB); -mmu.store_uint64(RB, RA | v); -RC = v; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, RS2 | v); +RDR = v; diff --git a/riscv/insns/amo_swap.h b/riscv/insns/amo_swap.h index 1995f83..0ee4ea2 100644 --- a/riscv/insns/amo_swap.h +++ b/riscv/insns/amo_swap.h @@ -1,4 +1,4 @@ require64; -reg_t v = mmu.load_uint64(RB); -mmu.store_uint64(RB, RA); -RC = v; +reg_t v = mmu.load_uint64(RS1); +mmu.store_uint64(RS1, RS2); +RDR = v; diff --git a/riscv/insns/amow_add.h b/riscv/insns/amow_add.h index fbf475d..a55ddf9 100644 --- a/riscv/insns/amow_add.h +++ b/riscv/insns/amow_add.h @@ -1,3 +1,3 @@ -reg_t v = mmu.load_int32(RB); -mmu.store_uint32(RB, RA + v); -RC = v; +reg_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, RS2 + v); +RDR = v; diff --git a/riscv/insns/amow_and.h b/riscv/insns/amow_and.h index 1166e86..f1670bd 100644 --- a/riscv/insns/amow_and.h +++ b/riscv/insns/amow_and.h @@ -1,3 +1,3 @@ -reg_t v = mmu.load_int32(RB); -mmu.store_uint32(RB, RA & v); -RC = v; +reg_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, RS2 & v); +RDR = v; diff --git a/riscv/insns/amow_max.h b/riscv/insns/amow_max.h index c5318e7..c4854d1 100644 --- a/riscv/insns/amow_max.h +++ b/riscv/insns/amow_max.h @@ -1,3 +1,3 @@ -int32_t v = mmu.load_int32(RB); -mmu.store_uint32(RB, std::max(int32_t(RA),v)); -RC = v; +int32_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, std::max(int32_t(RS2),v)); +RDR = v; diff --git a/riscv/insns/amow_maxu.h b/riscv/insns/amow_maxu.h index 9f5bf23..37219a8 100644 --- a/riscv/insns/amow_maxu.h +++ b/riscv/insns/amow_maxu.h @@ -1,3 +1,3 @@ -uint32_t v = mmu.load_int32(RB); -mmu.store_uint32(RB, std::max(uint32_t(RA),v)); -RC = v; +uint32_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, std::max(uint32_t(RS2),v)); +RDR = v; diff --git a/riscv/insns/amow_min.h b/riscv/insns/amow_min.h index a5abc48..ac13623 100644 --- a/riscv/insns/amow_min.h +++ b/riscv/insns/amow_min.h @@ -1,3 +1,3 @@ -int32_t v = mmu.load_int32(RB); -mmu.store_uint32(RB, std::min(int32_t(RA),v)); -RC = v; +int32_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, std::min(int32_t(RS2),v)); +RDR = v; diff --git a/riscv/insns/amow_minu.h b/riscv/insns/amow_minu.h index fe55d23..de3ee56 100644 --- a/riscv/insns/amow_minu.h +++ b/riscv/insns/amow_minu.h @@ -1,3 +1,3 @@ -uint32_t v = mmu.load_int32(RB); -mmu.store_uint32(RB, std::min(uint32_t(RA),v)); -RC = v; +uint32_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, std::min(uint32_t(RS2),v)); +RDR = v; diff --git a/riscv/insns/amow_or.h b/riscv/insns/amow_or.h index 09d105f..e569665 100644 --- a/riscv/insns/amow_or.h +++ b/riscv/insns/amow_or.h @@ -1,3 +1,3 @@ -reg_t v = mmu.load_int32(RB); -mmu.store_uint32(RB, RA | v); -RC = v; +reg_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, RS2 | v); +RDR = v; diff --git a/riscv/insns/amow_swap.h b/riscv/insns/amow_swap.h index 6aec206..c8b108a 100644 --- a/riscv/insns/amow_swap.h +++ b/riscv/insns/amow_swap.h @@ -1,3 +1,3 @@ -reg_t v = mmu.load_int32(RB); -mmu.store_uint32(RB, RA); -RC = v; +reg_t v = mmu.load_int32(RS1); +mmu.store_uint32(RS1, RS2); +RDR = v; diff --git a/riscv/insns/and.h b/riscv/insns/and.h index 305e541..a63e83f 100644 --- a/riscv/insns/and.h +++ b/riscv/insns/and.h @@ -1 +1 @@ -RC = RA & RB; +RDR = RS1 & RS2; diff --git a/riscv/insns/andi.h b/riscv/insns/andi.h index 86a045c..ada6657 100644 --- a/riscv/insns/andi.h +++ b/riscv/insns/andi.h @@ -1 +1 @@ -RA = IMM & RB; +RDI = IMM & RS1; diff --git a/riscv/insns/beq.h b/riscv/insns/beq.h index 320c33f..072b7b8 100644 --- a/riscv/insns/beq.h +++ b/riscv/insns/beq.h @@ -1,2 +1,2 @@ -if(cmp_trunc(RA) == cmp_trunc(RB)) +if(cmp_trunc(RS1) == cmp_trunc(RS2)) npc = BRANCH_TARGET; diff --git a/riscv/insns/bge.h b/riscv/insns/bge.h index 66db6b2..45dcc2e 100644 --- a/riscv/insns/bge.h +++ b/riscv/insns/bge.h @@ -1,2 +1,2 @@ -if(sreg_t(cmp_trunc(RA)) >= sreg_t(cmp_trunc(RB))) +if(sreg_t(cmp_trunc(RS1)) >= sreg_t(cmp_trunc(RS2))) npc = BRANCH_TARGET; diff --git a/riscv/insns/bgeu.h b/riscv/insns/bgeu.h index 52d6661..2ba3fa8 100644 --- a/riscv/insns/bgeu.h +++ b/riscv/insns/bgeu.h @@ -1,2 +1,2 @@ -if(cmp_trunc(RA) >= cmp_trunc(RB)) +if(cmp_trunc(RS1) >= cmp_trunc(RS2)) npc = BRANCH_TARGET; diff --git a/riscv/insns/blt.h b/riscv/insns/blt.h index 8d95127..3ffd20e 100644 --- a/riscv/insns/blt.h +++ b/riscv/insns/blt.h @@ -1,2 +1,2 @@ -if(sreg_t(cmp_trunc(RA)) < sreg_t(cmp_trunc(RB))) +if(sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2))) npc = BRANCH_TARGET; diff --git a/riscv/insns/bltu.h b/riscv/insns/bltu.h index 27deefe..186dcbe 100644 --- a/riscv/insns/bltu.h +++ b/riscv/insns/bltu.h @@ -1,2 +1,2 @@ -if(cmp_trunc(RA) < cmp_trunc(RB)) +if(cmp_trunc(RS1) < cmp_trunc(RS2)) npc = BRANCH_TARGET; diff --git a/riscv/insns/bne.h b/riscv/insns/bne.h index aee98f6..39b0b19 100644 --- a/riscv/insns/bne.h +++ b/riscv/insns/bne.h @@ -1,2 +1,2 @@ -if(cmp_trunc(RA) != cmp_trunc(RB)) +if(cmp_trunc(RS1) != cmp_trunc(RS2)) npc = BRANCH_TARGET; diff --git a/riscv/insns/c_eq_d.h b/riscv/insns/c_eq_d.h index cc7b77a..127e57e 100644 --- a/riscv/insns/c_eq_d.h +++ b/riscv/insns/c_eq_d.h @@ -1,3 +1,3 @@ require_fp; -RC = f64_eq(FRA, FRB); +RDR = f64_eq(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/c_eq_s.h b/riscv/insns/c_eq_s.h index 5500c4c..0a2ccd9 100644 --- a/riscv/insns/c_eq_s.h +++ b/riscv/insns/c_eq_s.h @@ -1,3 +1,3 @@ require_fp; -RC = f32_eq(FRA, FRB); +RDR = f32_eq(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/c_le_d.h b/riscv/insns/c_le_d.h index 2fe6f32..23f9703 100644 --- a/riscv/insns/c_le_d.h +++ b/riscv/insns/c_le_d.h @@ -1,3 +1,3 @@ require_fp; -RC = f64_le(FRA, FRB); +RDR = f64_le(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/c_le_s.h b/riscv/insns/c_le_s.h index e6e26b3..7350a9e 100644 --- a/riscv/insns/c_le_s.h +++ b/riscv/insns/c_le_s.h @@ -1,3 +1,3 @@ require_fp; -RC = f32_le(FRA, FRB); +RDR = f32_le(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/c_lt_d.h b/riscv/insns/c_lt_d.h index 3f3756d..77e7eec 100644 --- a/riscv/insns/c_lt_d.h +++ b/riscv/insns/c_lt_d.h @@ -1,3 +1,3 @@ require_fp; -RC = f64_lt(FRA, FRB); +RDR = f64_lt(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/c_lt_s.h b/riscv/insns/c_lt_s.h index aef7334..cdb4372 100644 --- a/riscv/insns/c_lt_s.h +++ b/riscv/insns/c_lt_s.h @@ -1,3 +1,3 @@ require_fp; -RC = f32_lt(FRA, FRB); +RDR = f32_lt(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/cvt_d_l.h index 808d20c..5faac2a 100644 --- a/riscv/insns/cvt_d_l.h +++ b/riscv/insns/cvt_d_l.h @@ -1,3 +1,3 @@ require_fp; -FRC = i64_to_f64(FRA); +FRDR = i64_to_f64(FRS1); set_fp_exceptions; diff --git a/riscv/insns/cvt_d_s.h b/riscv/insns/cvt_d_s.h index 69206e1..7a26f70 100644 --- a/riscv/insns/cvt_d_s.h +++ b/riscv/insns/cvt_d_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_to_f64(FRA); +FRDR = f32_to_f64(FRS1); set_fp_exceptions; diff --git a/riscv/insns/cvt_d_w.h b/riscv/insns/cvt_d_w.h index e1c36f2..67bc798 100644 --- a/riscv/insns/cvt_d_w.h +++ b/riscv/insns/cvt_d_w.h @@ -1,3 +1,3 @@ require_fp; -FRC = i32_to_f64(FRA); +FRDR = i32_to_f64(FRS1); set_fp_exceptions; diff --git a/riscv/insns/cvt_s_d.h b/riscv/insns/cvt_s_d.h index 0ee755e..56d6fe3 100644 --- a/riscv/insns/cvt_s_d.h +++ b/riscv/insns/cvt_s_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_to_f32(FRA); +FRDR = f64_to_f32(FRS1); set_fp_exceptions; diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/cvt_s_l.h index 66e4566..f5332f9 100644 --- a/riscv/insns/cvt_s_l.h +++ b/riscv/insns/cvt_s_l.h @@ -1,3 +1,3 @@ require_fp; -FRC = i64_to_f32(FRA); +FRDR = i64_to_f32(FRS1); set_fp_exceptions; diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/cvt_s_w.h index 5bbe61f..9db5386 100644 --- a/riscv/insns/cvt_s_w.h +++ b/riscv/insns/cvt_s_w.h @@ -1,3 +1,3 @@ require_fp; -FRC = i32_to_f32(FRA); +FRDR = i32_to_f32(FRS1); set_fp_exceptions; diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/cvtu_d_l.h index 808d20c..5faac2a 100644 --- a/riscv/insns/cvtu_d_l.h +++ b/riscv/insns/cvtu_d_l.h @@ -1,3 +1,3 @@ require_fp; -FRC = i64_to_f64(FRA); +FRDR = i64_to_f64(FRS1); set_fp_exceptions; diff --git a/riscv/insns/cvtu_d_w.h b/riscv/insns/cvtu_d_w.h index 1a61ad6..1b35e06 100644 --- a/riscv/insns/cvtu_d_w.h +++ b/riscv/insns/cvtu_d_w.h @@ -1,3 +1,3 @@ require_fp; -FRC = ui32_to_f64(FRA); +FRDR = ui32_to_f64(FRS1); set_fp_exceptions; diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/cvtu_s_l.h index 66e4566..f5332f9 100644 --- a/riscv/insns/cvtu_s_l.h +++ b/riscv/insns/cvtu_s_l.h @@ -1,3 +1,3 @@ require_fp; -FRC = i64_to_f32(FRA); +FRDR = i64_to_f32(FRS1); set_fp_exceptions; diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/cvtu_s_w.h index 8eaeca3..252e0cc 100644 --- a/riscv/insns/cvtu_s_w.h +++ b/riscv/insns/cvtu_s_w.h @@ -1,3 +1,3 @@ require_fp; -FRC = ui32_to_f32(FRA); +FRDR = ui32_to_f32(FRS1); set_fp_exceptions; diff --git a/riscv/insns/di.h b/riscv/insns/di.h index f555c2c..0f3adf9 100644 --- a/riscv/insns/di.h +++ b/riscv/insns/di.h @@ -1,4 +1,4 @@ require_supervisor; uint32_t temp = sr; set_sr(sr & ~SR_ET); -RC = temp; +RDR = temp; diff --git a/riscv/insns/div.h b/riscv/insns/div.h index f0c2d2b..2d6edfc 100644 --- a/riscv/insns/div.h +++ b/riscv/insns/div.h @@ -1,2 +1,2 @@ require64; -RC = sreg_t(RA) / sreg_t(RB); +RDR = sreg_t(RS1) / sreg_t(RS2); diff --git a/riscv/insns/div_d.h b/riscv/insns/div_d.h index 884effc..9902da6 100644 --- a/riscv/insns/div_d.h +++ b/riscv/insns/div_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_div(FRA, FRB); +FRDR = f64_div(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/div_s.h b/riscv/insns/div_s.h index b2d0869..99e343c 100644 --- a/riscv/insns/div_s.h +++ b/riscv/insns/div_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_div(FRA, FRB); +FRDR = f32_div(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/divu.h b/riscv/insns/divu.h index a4e3f4f..35eee14 100644 --- a/riscv/insns/divu.h +++ b/riscv/insns/divu.h @@ -1,2 +1,2 @@ require64; -RC = RA / RB; +RDR = RS1 / RS2; diff --git a/riscv/insns/divuw.h b/riscv/insns/divuw.h index 68f96a5..f52fe5a 100644 --- a/riscv/insns/divuw.h +++ b/riscv/insns/divuw.h @@ -1,2 +1,2 @@ -RC = sext32(uint32_t(RA)/uint32_t(RB)); +RDR = sext32(uint32_t(RS1)/uint32_t(RS2)); diff --git a/riscv/insns/divw.h b/riscv/insns/divw.h index e595c85..938478c 100644 --- a/riscv/insns/divw.h +++ b/riscv/insns/divw.h @@ -1,2 +1,2 @@ -RC = sext32(int32_t(RA)/int32_t(RB)); +RDR = sext32(int32_t(RS1)/int32_t(RS2)); diff --git a/riscv/insns/ei.h b/riscv/insns/ei.h index 75d79fe..f3e5207 100644 --- a/riscv/insns/ei.h +++ b/riscv/insns/ei.h @@ -1,4 +1,4 @@ require_supervisor; uint32_t temp = sr; set_sr(sr | SR_ET); -RC = temp; +RDR = temp; diff --git a/riscv/insns/jalr_c.h b/riscv/insns/jalr_c.h index 18b2508..dade874 100644 --- a/riscv/insns/jalr_c.h +++ b/riscv/insns/jalr_c.h @@ -1,3 +1,3 @@ uint32_t temp = npc; -npc = RA; -RC = temp; +npc = RS1; +RDR = temp; diff --git a/riscv/insns/l_d.h b/riscv/insns/l_d.h index 760cf98..8a06e3d 100644 --- a/riscv/insns/l_d.h +++ b/riscv/insns/l_d.h @@ -1,2 +1,2 @@ require_fp; -FRA = mmu.load_int64(RB+SIMM); +FRDI = mmu.load_int64(RS1+SIMM); diff --git a/riscv/insns/l_s.h b/riscv/insns/l_s.h index 1637fed..1e9bbf7 100644 --- a/riscv/insns/l_s.h +++ b/riscv/insns/l_s.h @@ -1,2 +1,2 @@ require_fp; -FRA = mmu.load_int32(RB+SIMM); +FRDI = mmu.load_int32(RS1+SIMM); diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h index ac8bf64..47e03d7 100644 --- a/riscv/insns/lb.h +++ b/riscv/insns/lb.h @@ -1 +1 @@ -RA = mmu.load_int8(RB+SIMM); +RDI = mmu.load_int8(RS1+SIMM); diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h index 522eb8f..e378871 100644 --- a/riscv/insns/lbu.h +++ b/riscv/insns/lbu.h @@ -1 +1 @@ -RA = mmu.load_uint8(RB+SIMM); +RDI = mmu.load_uint8(RS1+SIMM); diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h index 241af6a..9959d26 100644 --- a/riscv/insns/ld.h +++ b/riscv/insns/ld.h @@ -1,2 +1,2 @@ require64; -RA = mmu.load_int64(RB+SIMM); +RDI = mmu.load_int64(RS1+SIMM); diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h index e46ee14..830b673 100644 --- a/riscv/insns/lh.h +++ b/riscv/insns/lh.h @@ -1 +1 @@ -RA = mmu.load_int16(RB+SIMM); +RDI = mmu.load_int16(RS1+SIMM); diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h index 1f22423..961c427 100644 --- a/riscv/insns/lhu.h +++ b/riscv/insns/lhu.h @@ -1 +1 @@ -RA = mmu.load_uint16(RB+SIMM); +RDI = mmu.load_uint16(RS1+SIMM); diff --git a/riscv/insns/lui.h b/riscv/insns/lui.h index 0eb14bc..20a0af8 100644 --- a/riscv/insns/lui.h +++ b/riscv/insns/lui.h @@ -1 +1 @@ -RA = sext32(BIGIMM << IMM_BITS); +RDI = sext32(BIGIMM << IMM_BITS); diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h index e1f56fe..6bd2646 100644 --- a/riscv/insns/lw.h +++ b/riscv/insns/lw.h @@ -1 +1 @@ -RA = mmu.load_int32(RB+SIMM); +RDI = mmu.load_int32(RS1+SIMM); diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h index 311292d..3c597af 100644 --- a/riscv/insns/lwu.h +++ b/riscv/insns/lwu.h @@ -1 +1 @@ -RA = mmu.load_uint32(RB+SIMM); +RDI = mmu.load_uint32(RS1+SIMM); diff --git a/riscv/insns/madd_d.h b/riscv/insns/madd_d.h index e1b9206..c9d6318 100644 --- a/riscv/insns/madd_d.h +++ b/riscv/insns/madd_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_mulAdd(FRA, FRB, FRD); +FRDR = f64_mulAdd(FRS1, FRS2, FRS3); set_fp_exceptions; diff --git a/riscv/insns/madd_s.h b/riscv/insns/madd_s.h index 3433adf..49f4861 100644 --- a/riscv/insns/madd_s.h +++ b/riscv/insns/madd_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_mulAdd(FRA, FRB, FRD); +FRDR = f32_mulAdd(FRS1, FRS2, FRS3); set_fp_exceptions; diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h index 088480c..1d6b4d1 100644 --- a/riscv/insns/mfcr.h +++ b/riscv/insns/mfcr.h @@ -1,6 +1,6 @@ reg_t val; -switch(insn.rtype.rb) +switch(insn.rtype.rs2) { case 0: val = fsr; @@ -18,4 +18,4 @@ switch(insn.rtype.rb) val = -1; } -RC = gprlen == 64 ? val : sext32(val); +RDR = gprlen == 64 ? val : sext32(val); diff --git a/riscv/insns/mff_d.h b/riscv/insns/mff_d.h index e2e8415..1f0182e 100644 --- a/riscv/insns/mff_d.h +++ b/riscv/insns/mff_d.h @@ -1,3 +1,3 @@ require64; require_fp; -RC = FRA; +RDR = FRS1; diff --git a/riscv/insns/mff_s.h b/riscv/insns/mff_s.h index f92c935..a258aa0 100644 --- a/riscv/insns/mff_s.h +++ b/riscv/insns/mff_s.h @@ -1,2 +1,2 @@ require_fp; -RC = sext32(FRA); +RDR = sext32(FRS1); diff --git a/riscv/insns/mffh_d.h b/riscv/insns/mffh_d.h index b466f60..45dd36a 100644 --- a/riscv/insns/mffh_d.h +++ b/riscv/insns/mffh_d.h @@ -1,2 +1,2 @@ require_fp; -RC = sext32(FRA >> 32); +RDR = sext32(FRS1 >> 32); diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h index 3416db1..0060957 100644 --- a/riscv/insns/mfpcr.h +++ b/riscv/insns/mfpcr.h @@ -2,7 +2,7 @@ require_supervisor; reg_t val; -switch(insn.rtype.rb) +switch(insn.rtype.rs2) { case 0: val = sr; @@ -42,4 +42,4 @@ switch(insn.rtype.rb) val = -1; } -RC = gprlen == 64 ? val : sext32(val); +RDR = gprlen == 64 ? val : sext32(val); diff --git a/riscv/insns/msub_d.h b/riscv/insns/msub_d.h index 747cacc..939baca 100644 --- a/riscv/insns/msub_d.h +++ b/riscv/insns/msub_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_mulAdd(FRA, FRB, FRD ^ (uint64_t)INT64_MIN); +FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN); set_fp_exceptions; diff --git a/riscv/insns/msub_s.h b/riscv/insns/msub_s.h index 60f10a4..b808951 100644 --- a/riscv/insns/msub_s.h +++ b/riscv/insns/msub_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_mulAdd(FRA, FRB, FRD ^ (uint32_t)INT32_MIN); +FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN); set_fp_exceptions; diff --git a/riscv/insns/mtcr.h b/riscv/insns/mtcr.h index d7b2b17..ba55899 100644 --- a/riscv/insns/mtcr.h +++ b/riscv/insns/mtcr.h @@ -1,10 +1,10 @@ -switch(insn.rtype.rb) +switch(insn.rtype.rs2) { case 0: - set_fsr(RA); + set_fsr(RS1); break; case 29: - tid = RA; + tid = RS1; break; } diff --git a/riscv/insns/mtf_d.h b/riscv/insns/mtf_d.h index 4d39833..6777689 100644 --- a/riscv/insns/mtf_d.h +++ b/riscv/insns/mtf_d.h @@ -1,3 +1,3 @@ require64; require_fp; -FRC = RA; +FRDR = RS1; diff --git a/riscv/insns/mtf_s.h b/riscv/insns/mtf_s.h index 723a2f7..a1c22fd 100644 --- a/riscv/insns/mtf_s.h +++ b/riscv/insns/mtf_s.h @@ -1,2 +1,2 @@ require_fp; -FRC = RA; +FRDR = RS1; diff --git a/riscv/insns/mtflh_d.h b/riscv/insns/mtflh_d.h index 4e33f39..c48c726 100644 --- a/riscv/insns/mtflh_d.h +++ b/riscv/insns/mtflh_d.h @@ -1,2 +1,2 @@ require_fp; -FRC = (RA & 0x00000000FFFFFFFF) | (RB << 32); +FRDR = (RS1 & 0x00000000FFFFFFFF) | (RS2 << 32); diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h index 79e28bf..bcc613a 100644 --- a/riscv/insns/mtpcr.h +++ b/riscv/insns/mtpcr.h @@ -1,33 +1,33 @@ require_supervisor; -switch(insn.rtype.rb) +switch(insn.rtype.rs2) { case 0: - set_sr(RA); + set_sr(RS1); break; case 1: - epc = RA; + epc = RS1; break; case 3: - ebase = RA & ~0xFFF; + ebase = RS1 & ~0xFFF; break; case 4: - count = RA; + count = RS1; break; case 5: interrupts_pending &= ~(1 << TIMER_IRQ); - compare = RA; + compare = RS1; break; case 16: - tohost = RA; - sim->set_tohost(RA); + tohost = RS1; + sim->set_tohost(RS1); break; case 24: - pcr_k0 = RA; + pcr_k0 = RS1; break; case 25: - pcr_k1 = RA; + pcr_k1 = RS1; break; } diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h index 9c81285..226873f 100644 --- a/riscv/insns/mul.h +++ b/riscv/insns/mul.h @@ -1,2 +1,2 @@ require64; -RC = RA * RB; +RDR = RS1 * RS2; diff --git a/riscv/insns/mul_d.h b/riscv/insns/mul_d.h index d16e6c5..75c7b94 100644 --- a/riscv/insns/mul_d.h +++ b/riscv/insns/mul_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_mul(FRA, FRB); +FRDR = f64_mul(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/mul_s.h b/riscv/insns/mul_s.h index d700d84..5c1397c 100644 --- a/riscv/insns/mul_s.h +++ b/riscv/insns/mul_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_mul(FRA, FRB); +FRDR = f32_mul(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/mulh.h b/riscv/insns/mulh.h index 2d7ca4c..c4fead2 100644 --- a/riscv/insns/mulh.h +++ b/riscv/insns/mulh.h @@ -1,4 +1,4 @@ require64; -int64_t rb = RA; -int64_t ra = RB; -RC = (int128_t(rb) * int128_t(ra)) >> 64; +int64_t rb = RS1; +int64_t ra = RS2; +RDR = (int128_t(rb) * int128_t(ra)) >> 64; diff --git a/riscv/insns/mulhu.h b/riscv/insns/mulhu.h index 45e9704..1ce0252 100644 --- a/riscv/insns/mulhu.h +++ b/riscv/insns/mulhu.h @@ -1,2 +1,2 @@ require64; -RC = (uint128_t(RA) * uint128_t(RB)) >> 64; +RDR = (uint128_t(RS1) * uint128_t(RS2)) >> 64; diff --git a/riscv/insns/mulhuw.h b/riscv/insns/mulhuw.h index 9f3de3f..c2a082d 100644 --- a/riscv/insns/mulhuw.h +++ b/riscv/insns/mulhuw.h @@ -1,2 +1,2 @@ -RC = sext32((RA * RB) >> 32); +RDR = sext32((RS1 * RS2) >> 32); diff --git a/riscv/insns/mulhw.h b/riscv/insns/mulhw.h index 90a17be..7becbfe 100644 --- a/riscv/insns/mulhw.h +++ b/riscv/insns/mulhw.h @@ -1,2 +1,2 @@ -RC = sext32((sreg_t(RA) * sreg_t(RB)) >> 32); +RDR = sext32((sreg_t(RS1) * sreg_t(RS2)) >> 32); diff --git a/riscv/insns/mulw.h b/riscv/insns/mulw.h index d999172..c483fb6 100644 --- a/riscv/insns/mulw.h +++ b/riscv/insns/mulw.h @@ -1,2 +1,2 @@ -RC = sext32(RA * RB); +RDR = sext32(RS1 * RS2); diff --git a/riscv/insns/nmadd_d.h b/riscv/insns/nmadd_d.h index 73ab2bf..1cdebd3 100644 --- a/riscv/insns/nmadd_d.h +++ b/riscv/insns/nmadd_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_mulAdd(FRA, FRB, FRD) ^ (uint64_t)INT64_MIN; +FRDR = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN; set_fp_exceptions; diff --git a/riscv/insns/nmadd_s.h b/riscv/insns/nmadd_s.h index c060355..b0b7021 100644 --- a/riscv/insns/nmadd_s.h +++ b/riscv/insns/nmadd_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_mulAdd(FRA, FRB, FRD) ^ (uint32_t)INT32_MIN; +FRDR = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN; set_fp_exceptions; diff --git a/riscv/insns/nmsub_d.h b/riscv/insns/nmsub_d.h index 0c06f47..1e010c8 100644 --- a/riscv/insns/nmsub_d.h +++ b/riscv/insns/nmsub_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_mulAdd(FRA, FRB, FRD ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN; +FRDR = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN; set_fp_exceptions; diff --git a/riscv/insns/nmsub_s.h b/riscv/insns/nmsub_s.h index d9fe109..9818dc7 100644 --- a/riscv/insns/nmsub_s.h +++ b/riscv/insns/nmsub_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_mulAdd(FRA, FRB, FRD ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN; +FRDR = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN; set_fp_exceptions; diff --git a/riscv/insns/nor.h b/riscv/insns/nor.h index 5bb7e89..a3ba7d1 100644 --- a/riscv/insns/nor.h +++ b/riscv/insns/nor.h @@ -1 +1 @@ -RC = ~(RA | RB); +RDR = ~(RS1 | RS2); diff --git a/riscv/insns/or.h b/riscv/insns/or.h index d88c9f8..ef27ba6 100644 --- a/riscv/insns/or.h +++ b/riscv/insns/or.h @@ -1 +1 @@ -RC = RA | RB; +RDR = RS1 | RS2; diff --git a/riscv/insns/ori.h b/riscv/insns/ori.h index 2fab937..d49c8c1 100644 --- a/riscv/insns/ori.h +++ b/riscv/insns/ori.h @@ -1 +1 @@ -RA = IMM | RB; +RDI = IMM | RS1; diff --git a/riscv/insns/rdnpc.h b/riscv/insns/rdnpc.h index 95e528a..254512c 100644 --- a/riscv/insns/rdnpc.h +++ b/riscv/insns/rdnpc.h @@ -1 +1 @@ -RC = npc; +RDR = npc; diff --git a/riscv/insns/rem.h b/riscv/insns/rem.h index dfece43..9192428 100644 --- a/riscv/insns/rem.h +++ b/riscv/insns/rem.h @@ -1,2 +1,2 @@ require64; -RC = sreg_t(RA) % sreg_t(RB); +RDR = sreg_t(RS1) % sreg_t(RS2); diff --git a/riscv/insns/remu.h b/riscv/insns/remu.h index e8ee6b1..2f40aaa 100644 --- a/riscv/insns/remu.h +++ b/riscv/insns/remu.h @@ -1,2 +1,2 @@ require64; -RC = RA % RB; +RDR = RS1 % RS2; diff --git a/riscv/insns/remuw.h b/riscv/insns/remuw.h index d028488..26decf2 100644 --- a/riscv/insns/remuw.h +++ b/riscv/insns/remuw.h @@ -1,2 +1,2 @@ -RC = sext32(uint32_t(RA) % uint32_t(RB)); +RDR = sext32(uint32_t(RS1) % uint32_t(RS2)); diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h index 1bb3051..83bf147 100644 --- a/riscv/insns/remw.h +++ b/riscv/insns/remw.h @@ -1,2 +1,2 @@ -RC = sext32(int32_t(RA) % int32_t(RB)); +RDR = sext32(int32_t(RS1) % int32_t(RS2)); diff --git a/riscv/insns/s_d.h b/riscv/insns/s_d.h index d1c8037..4c9c466 100644 --- a/riscv/insns/s_d.h +++ b/riscv/insns/s_d.h @@ -1,2 +1,2 @@ require_fp; -mmu.store_uint64(RB+SIMM, FRA); +mmu.store_uint64(RS1+SIMM, FRS2); diff --git a/riscv/insns/s_s.h b/riscv/insns/s_s.h index 837c258..384246f 100644 --- a/riscv/insns/s_s.h +++ b/riscv/insns/s_s.h @@ -1,2 +1,2 @@ require_fp; -mmu.store_uint32(RB+SIMM, FRA); +mmu.store_uint32(RS1+SIMM, FRS2); diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h index 618140d..5a2110f 100644 --- a/riscv/insns/sb.h +++ b/riscv/insns/sb.h @@ -1 +1 @@ -mmu.store_uint8(RB+SIMM, RA); +mmu.store_uint8(RS1+SIMM, RS2); diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h index 6a698ee..587df8d 100644 --- a/riscv/insns/sd.h +++ b/riscv/insns/sd.h @@ -1,2 +1,2 @@ require64; -mmu.store_uint64(RB+SIMM, RA); +mmu.store_uint64(RS1+SIMM, RS2); diff --git a/riscv/insns/sgninj_d.h b/riscv/insns/sgninj_d.h index 8bca56a..b1722da 100644 --- a/riscv/insns/sgninj_d.h +++ b/riscv/insns/sgninj_d.h @@ -1,2 +1,2 @@ require_fp; -FRC = (FRA &~ INT64_MIN) | (FRB & INT64_MIN); +FRDR = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN); diff --git a/riscv/insns/sgninj_s.h b/riscv/insns/sgninj_s.h index b688177..2df0b94 100644 --- a/riscv/insns/sgninj_s.h +++ b/riscv/insns/sgninj_s.h @@ -1,2 +1,2 @@ require_fp; -FRC = (FRA &~ (uint32_t)INT32_MIN) | (FRB & (uint32_t)INT32_MIN); +FRDR = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN); diff --git a/riscv/insns/sgninjn_d.h b/riscv/insns/sgninjn_d.h index c526735..90c7ae9 100644 --- a/riscv/insns/sgninjn_d.h +++ b/riscv/insns/sgninjn_d.h @@ -1,2 +1,2 @@ require_fp; -FRC = (FRA &~ INT64_MIN) | ((~FRB) & INT64_MIN); +FRDR = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN); diff --git a/riscv/insns/sgninjn_s.h b/riscv/insns/sgninjn_s.h index 80dd7e8..7be7b46 100644 --- a/riscv/insns/sgninjn_s.h +++ b/riscv/insns/sgninjn_s.h @@ -1,2 +1,2 @@ require_fp; -FRC = (FRA &~ (uint32_t)INT32_MIN) | ((~FRB) & (uint32_t)INT32_MIN); +FRDR = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN); diff --git a/riscv/insns/sgnmul_d.h b/riscv/insns/sgnmul_d.h index c30dcea..8e55850 100644 --- a/riscv/insns/sgnmul_d.h +++ b/riscv/insns/sgnmul_d.h @@ -1,2 +1,2 @@ require_fp; -FRC = FRA ^ (FRB & INT64_MIN); +FRDR = FRS1 ^ (FRS2 & INT64_MIN); diff --git a/riscv/insns/sgnmul_s.h b/riscv/insns/sgnmul_s.h index 6640b31..e651888 100644 --- a/riscv/insns/sgnmul_s.h +++ b/riscv/insns/sgnmul_s.h @@ -1,2 +1,2 @@ require_fp; -FRC = FRA ^ (FRB & (uint32_t)INT32_MIN); +FRDR = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN); diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h index e0fdc0a..bbc2bda 100644 --- a/riscv/insns/sh.h +++ b/riscv/insns/sh.h @@ -1 +1 @@ -mmu.store_uint16(RB+SIMM, RA); +mmu.store_uint16(RS1+SIMM, RS2); diff --git a/riscv/insns/sll.h b/riscv/insns/sll.h index 7e81e6b..59da49d 100644 --- a/riscv/insns/sll.h +++ b/riscv/insns/sll.h @@ -1,2 +1,2 @@ require64; -RC = RB << (RA & 0x3F); +RDR = RS2 << (RS1 & 0x3F); diff --git a/riscv/insns/slli.h b/riscv/insns/slli.h index 606512b..33e23aa 100644 --- a/riscv/insns/slli.h +++ b/riscv/insns/slli.h @@ -1,2 +1,2 @@ require64; -RA = RB << SHAMT; +RDI = RS1 << SHAMT; diff --git a/riscv/insns/slliw.h b/riscv/insns/slliw.h index c8b345c..8546977 100644 --- a/riscv/insns/slliw.h +++ b/riscv/insns/slliw.h @@ -1 +1 @@ -RA = sext32(RB << SHAMTW); +RDI = sext32(RS1 << SHAMTW); diff --git a/riscv/insns/sllw.h b/riscv/insns/sllw.h index f694a2f..3d96b0f 100644 --- a/riscv/insns/sllw.h +++ b/riscv/insns/sllw.h @@ -1 +1 @@ -RC = sext32(RB << (RA & 0x1F)); +RDR = sext32(RS2 << (RS1 & 0x1F)); diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h index ccc1d44..6511f42 100644 --- a/riscv/insns/slt.h +++ b/riscv/insns/slt.h @@ -1 +1 @@ -RC = sreg_t(cmp_trunc(RA)) < sreg_t(cmp_trunc(RB)); +RDR = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2)); diff --git a/riscv/insns/slti.h b/riscv/insns/slti.h index a5ef31e..6204619 100644 --- a/riscv/insns/slti.h +++ b/riscv/insns/slti.h @@ -1 +1 @@ -RA = sreg_t(cmp_trunc(RB)) < sreg_t(cmp_trunc(SIMM)); +RDI = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(SIMM)); diff --git a/riscv/insns/sltiu.h b/riscv/insns/sltiu.h index a09f3ec..b7c8ce6 100644 --- a/riscv/insns/sltiu.h +++ b/riscv/insns/sltiu.h @@ -1 +1 @@ -RA = cmp_trunc(RB) < cmp_trunc(SIMM); +RDI = cmp_trunc(RS1) < cmp_trunc(SIMM); diff --git a/riscv/insns/sltu.h b/riscv/insns/sltu.h index 32fc94d..1d4ebe6 100644 --- a/riscv/insns/sltu.h +++ b/riscv/insns/sltu.h @@ -1 +1 @@ -RC = cmp_trunc(RA) < cmp_trunc(RB); +RDR = cmp_trunc(RS1) < cmp_trunc(RS2); diff --git a/riscv/insns/sqrt_d.h b/riscv/insns/sqrt_d.h index fdfc19a..99ffa18 100644 --- a/riscv/insns/sqrt_d.h +++ b/riscv/insns/sqrt_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_sqrt(FRA); +FRDR = f64_sqrt(FRS1); set_fp_exceptions; diff --git a/riscv/insns/sqrt_s.h b/riscv/insns/sqrt_s.h index 5f2968c..12c8160 100644 --- a/riscv/insns/sqrt_s.h +++ b/riscv/insns/sqrt_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_sqrt(FRA); +FRDR = f32_sqrt(FRS1); set_fp_exceptions; diff --git a/riscv/insns/sra.h b/riscv/insns/sra.h index e01fcd5..6dfde0f 100644 --- a/riscv/insns/sra.h +++ b/riscv/insns/sra.h @@ -1,2 +1,2 @@ require64; -RC = sreg_t(RB) >> (RA & 0x3F); +RDR = sreg_t(RS2) >> (RS1 & 0x3F); diff --git a/riscv/insns/srai.h b/riscv/insns/srai.h index 12a67a3..b2026bb 100644 --- a/riscv/insns/srai.h +++ b/riscv/insns/srai.h @@ -1,2 +1,2 @@ require64; -RA = sreg_t(RB) >> SHAMT; +RDI = sreg_t(RS1) >> SHAMT; diff --git a/riscv/insns/sraiw.h b/riscv/insns/sraiw.h index 7289347..0831b14 100644 --- a/riscv/insns/sraiw.h +++ b/riscv/insns/sraiw.h @@ -1 +1 @@ -RA = sext32(sreg_t(RB) >> SHAMTW); +RDI = sext32(sreg_t(RS1) >> SHAMTW); diff --git a/riscv/insns/sraw.h b/riscv/insns/sraw.h index 8e9aa88..111f632 100644 --- a/riscv/insns/sraw.h +++ b/riscv/insns/sraw.h @@ -1 +1 @@ -RC = sext32(sreg_t(RB) >> (RA & 0x1F)); +RDR = sext32(sreg_t(RS2) >> (RS1 & 0x1F)); diff --git a/riscv/insns/srl.h b/riscv/insns/srl.h index ec6fee8..1512be9 100644 --- a/riscv/insns/srl.h +++ b/riscv/insns/srl.h @@ -1,2 +1,2 @@ require64; -RC = RB >> (RA & 0x3F); +RDR = RS2 >> (RS1 & 0x3F); diff --git a/riscv/insns/srli.h b/riscv/insns/srli.h index d7bc2b4..29a97a2 100644 --- a/riscv/insns/srli.h +++ b/riscv/insns/srli.h @@ -1,2 +1,2 @@ require64; -RA = RB >> SHAMT; +RDI = RS1 >> SHAMT; diff --git a/riscv/insns/srliw.h b/riscv/insns/srliw.h index 6534a89..5513a5a 100644 --- a/riscv/insns/srliw.h +++ b/riscv/insns/srliw.h @@ -1 +1 @@ -RA = sext32((uint32_t)RB >> SHAMTW); +RDI = sext32((uint32_t)RS1 >> SHAMTW); diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h index c523b59..2d9de89 100644 --- a/riscv/insns/srlw.h +++ b/riscv/insns/srlw.h @@ -1 +1 @@ -RC = sext32((uint32_t)RB >> (RA & 0x1F)); +RDR = sext32((uint32_t)RS2 >> (RS1 & 0x1F)); diff --git a/riscv/insns/sub.h b/riscv/insns/sub.h index e7ac407..005b66f 100644 --- a/riscv/insns/sub.h +++ b/riscv/insns/sub.h @@ -1,2 +1,2 @@ require64; -RC = RA - RB; +RDR = RS1 - RS2; diff --git a/riscv/insns/sub_d.h b/riscv/insns/sub_d.h index 023a1f3..2099732 100644 --- a/riscv/insns/sub_d.h +++ b/riscv/insns/sub_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_sub(FRA, FRB); +FRDR = f64_sub(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/sub_s.h b/riscv/insns/sub_s.h index fd83da0..e28f042 100644 --- a/riscv/insns/sub_s.h +++ b/riscv/insns/sub_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_sub(FRA, FRB); +FRDR = f32_sub(FRS1, FRS2); set_fp_exceptions; diff --git a/riscv/insns/subw.h b/riscv/insns/subw.h index 60bcf27..9dd7114 100644 --- a/riscv/insns/subw.h +++ b/riscv/insns/subw.h @@ -1,2 +1,2 @@ -RC = sext32(RA - RB); +RDR = sext32(RS1 - RS2); diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h index b4e3b3d..e644e16 100644 --- a/riscv/insns/sw.h +++ b/riscv/insns/sw.h @@ -1 +1 @@ -mmu.store_uint32(RB+SIMM, RA); +mmu.store_uint32(RS1+SIMM, RS2); diff --git a/riscv/insns/trunc_l_d.h b/riscv/insns/trunc_l_d.h index 0fad400..e71957b 100644 --- a/riscv/insns/trunc_l_d.h +++ b/riscv/insns/trunc_l_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_to_i64_r_minMag(FRA,true); +FRDR = f64_to_i64_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/trunc_l_s.h b/riscv/insns/trunc_l_s.h index 5d5a940..1d48192 100644 --- a/riscv/insns/trunc_l_s.h +++ b/riscv/insns/trunc_l_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_to_i64_r_minMag(FRA,true); +FRDR = f32_to_i64_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/trunc_w_d.h b/riscv/insns/trunc_w_d.h index b91640a..2fea3dc 100644 --- a/riscv/insns/trunc_w_d.h +++ b/riscv/insns/trunc_w_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_to_i32_r_minMag(FRA,true); +FRDR = f64_to_i32_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/trunc_w_s.h b/riscv/insns/trunc_w_s.h index 73974d1..e70f9c4 100644 --- a/riscv/insns/trunc_w_s.h +++ b/riscv/insns/trunc_w_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_to_i32_r_minMag(FRA,true); +FRDR = f32_to_i32_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/truncu_l_d.h b/riscv/insns/truncu_l_d.h index 0fad400..e71957b 100644 --- a/riscv/insns/truncu_l_d.h +++ b/riscv/insns/truncu_l_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_to_i64_r_minMag(FRA,true); +FRDR = f64_to_i64_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/truncu_l_s.h b/riscv/insns/truncu_l_s.h index 5d5a940..1d48192 100644 --- a/riscv/insns/truncu_l_s.h +++ b/riscv/insns/truncu_l_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_to_i64_r_minMag(FRA,true); +FRDR = f32_to_i64_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/truncu_w_d.h b/riscv/insns/truncu_w_d.h index 255fba5..bb674f6 100644 --- a/riscv/insns/truncu_w_d.h +++ b/riscv/insns/truncu_w_d.h @@ -1,3 +1,3 @@ require_fp; -FRC = f64_to_ui32_r_minMag(FRA,true); +FRDR = f64_to_ui32_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/truncu_w_s.h b/riscv/insns/truncu_w_s.h index 337b9ea..d85f9e5 100644 --- a/riscv/insns/truncu_w_s.h +++ b/riscv/insns/truncu_w_s.h @@ -1,3 +1,3 @@ require_fp; -FRC = f32_to_ui32_r_minMag(FRA,true); +FRDR = f32_to_ui32_r_minMag(FRS1,true); set_fp_exceptions; diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h index 9d02447..f11738a 100644 --- a/riscv/insns/xor.h +++ b/riscv/insns/xor.h @@ -1 +1 @@ -RC = RA ^ RB; +RDR = RS1 ^ RS2; diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h index 5ca4637..fcf9042 100644 --- a/riscv/insns/xori.h +++ b/riscv/insns/xori.h @@ -1 +1 @@ -RA = IMM ^ RB; +RDI = IMM ^ RS1; |