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rocket-tools/riscv-isa-sim.git
confprec
cs250
csr-init-fixes
cycleh
debug_rom
debug_rom_fence
device_flags
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dts_parsing
dynamic
eos18-bringup
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nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
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plic_uart_v1
priv-1.10
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rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
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test
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path:
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riscv
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insns
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srl.h
blob: 1512be95135b2872266343ed9a5a78c571fd2475 (
plain
)
1
2
require64
;
RDR
=
RS2
>> (
RS1
&
0x3F
);
