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rocket-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
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eos18-bringup
factor-out-macros
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plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
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sparse-mem
speed2
speedup-hacks
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test
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path:
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/
riscv
/
insns
/
sraw.h
blob: 8e9aa8825f14dd27ffccb400ad539282fa940ea0 (
plain
)
1
RC
=
sext32
(
sreg_t
(
RB
) >> (
RA
&
0x1F
));
