index
:
rocket-tools/riscv-isa-sim.git
confprec
cs250
cycleh
debug_rom
debug_rom_fence
device_flags
dtm_reset_error
dts_parsing
dynamic
eos18-bringup
factor-out-macros
fix-bf16
force-rtti
fp-encoding
heterogeneous_mc
hwachav4
increase-stack-size
itrigger-etrigger-cleanup
load_reservation_set_size
log-commits-faster
master
mmio-hack
mvp
no_progbuf
no_progbuf2
nolibfdt
p-ext-0.5.2
plctlab-plct-zce-fix2
plic-clint-endian
plic_uart_v1
priv-1.10
private-l1-caches
pte-info-and-delegation
remove-tests
rivosinc-etrigger_fix_exception_match
rva-profile-support
simplify-misaligned
sodor
sparse-mem
speedup-hacks
static-link
test
tmp
trigger_priority
tweak_debug_rom
whole-archive
sifive/rvv0.9-phase2
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range
path:
root
/
riscv
/
insns
/
mtcr.h
blob: d7b2b17eb2b1c9d6c689528ad0357da562f46bb9 (
plain
)
1
2
3
4
5
6
7
8
9
10
switch
(
insn
.
rtype
.
rb
)
{
case
0
:
set_fsr
(
RA
);
break
;
case
29
:
tid
=
RA
;
break
;
}