Because using two booleans gives the impression that there are four
possibilities. Since hideleg is itself masked by mideleg, there are
effectively only three choices, so make that explicit via enum.

Since hideleg is now masked by mideleg, there's no need to separately
consider mideleg here.

According to spec clarification:
https://github.com/riscv/riscv-isa-manual/pull/771

This has no functional effect today, because all the active bits of
hideleg are tied to 1 inside mideleg.

According to spec clarification:
https://github.com/riscv/riscv-isa-manual/pull/771

This has no functional effect today, because all the active bits of
these CSRs are tied to 1 inside mideleg.

Fix #820 by relocating definition of P and require macros

Avoids namespace conflicts with Boost.

Fixes #820 in a better way.

This reverts commit 4f129845.

Set GVA properly on breakpoint traps

So I can fix breakpoints next to properly report gva.

Since breakpoint will need it soon.

Improves log because it now shows "trap_breakpoint" instead of "trap #3".

Krypto 1.0 changes: Entropy source CSR, name.
List scalar crypto instruction groupings, as there is no single K extension.

Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>

This will enable the Krypto changes in #846 to apply cleanly.

This removes the encodings for N-extension (user interrupts) which
were never implemented in Spike; also fixes the encoding of
sfence.w.inval and sfence.inval.ir, confirmed by @daniellustig:
https://github.com/riscv-software-src/riscv-isa-sim/pull/846#discussion_r741437419

This was generated from
https://github.com/riscv/riscv-opcodes/commit/70c120b5464d0a77491f07e5d66c4523d63a86a4
which I created to get the generated encoding.h to most closely match
what Spike already had; see https://github.com/riscv/riscv-opcodes/pull/87

Co-authored-by: Markku-Juhani O. Saarinen <mjos@mjos.fi>

Error log:
  libriscv.a(processor.o): In function `state_t::reset(processor_t*, unsigned long)':
  .../_build/../riscv/processor.cc:509: undefined reference to `state_t::num_triggers'
  collect2: error: ld returned 1 exit status
  Makefile:349: recipe for target 'spike-log-parser' failed

Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>

After excuting vector load/store whole register instructions,
	spike would be crashed when excuted the next vector instruction.

Signed-off-by: Eric Tang <tangxingxin1008@gmail.com>

Stringstream is very slow, so avoid using it in cases where simply
using a string doesn't make the code too ugly.

Stringstream is very slow; it's faster to manipulate strings instead.

Also, handle the underscore-dot replacement as a preprocessing step,
rather than doing it redundantly every time.

Optimize the hash functions for RISC-V instruction encodings.  This is
only a perf optimization; instructions that don't adhere to RISC-V
standard practice will still disassemble correctly, just more slowly.

Resolves #820

* Added ZMMUL extension

* Splitted P-ext to its zeds

* Typo fix

We were not properly checking for Machine-level or Supervisor-level
CSR accessibility.

No functional change, but only because all float_csr_t have User-level
permissions today.

Fix sharing of vxsat between V and P extensions

Any such instruction should have taken an illegal instruction
exception first.

This would have helped catch #823 where P-extension instructions were
setting vxsat=1 (and mstatus.VS=Dirty) without first checking for
mstatus.VS!=Off.

Part of #823.

Since its rules will need to be different than other vector CSRs
(coming next).

No functional change intended.

Any instruction that may write vxsat will take an illegal instruction
exception if mstatus.VS exists and is Off.

In Spike today, mstatus.VS exists iff misa.V=1, which is true iff the
--isa string enables the V extension.

I went through the riscv-p-spec looking for "OV = 1" and added this
behavior to every matching instruction.

See #823 for discussion.

This has no functional effect (yet), but will once I change the
P-extension instructions that access vxsat to properly consider
mstatus.VS.

No functional change intended.

This will allow me to consider whether the given field exists at all,
which I will eventually use to fix #823.

So I can add specialized methods to base_status_csr_t next, for use
from within sstatus_csr_t.

As requested by @marcfedorow:
https://github.com/riscv-software-src/riscv-isa-sim/issues/823#issuecomment-936509476

If mstatus.VS exists (i.e. Vector extension is enabled), it will no
longer be set to Dirty unless the instruction actually sets vxsat.

The mstatus.VS change only affects instructions in the P extension,
since Vector instructions will write other vector state and therefore
still set mstatus.VS=Dirty.

This also affects the commit log. Instructions that don't saturate
will no longer show a write to vxsat.