1. Jun 29, 2020
  2. Jun 20, 2020
    • Anup Patel's avatar
      include: Bump-up version to 0.8 · a98258d0
      Anup Patel authored
      
      
      This patch updates OpenSBI version to 0.8 as part of
      release preparation.
      
      Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
      a98258d0
    • Anup Patel's avatar
      lib: Don't return any invalid error from SBI ecall · 23141019
      Anup Patel authored
      
      
      We should only return valid error codes from SBI ecalls as
      defined by the RISC-V SBI spec.
      
      To achieve this:
      1. We use SBI_Exxxx defines for OpenSBI internal errors with
         error values starting from -1000
      2. We use SBI_ERR_xxxx defines for errors defined by SBI spec
      3. We map some of the SBI_Exxxx defines to SBI_ERR_xxxx defines
         which are semantically same
      4. We throw a error print and force return error code to
         SBI_ERR_FAILED in sbi_ecall_handler() if we see an invalid
         error code being returned to S-mode
      
      Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
      Reviewed-by: default avatarAtish Patra <atish.patra@wdc.com>
      23141019
    • Liush's avatar
      lib: sbi: Fix 32/64 bits variable compatibility · 9bd5f8f1
      Liush authored
      
      
      On RV64,"unsigned long" is 64bit and "unsigned int" is 32bit. So in
      function "pmp_get" and "pmp_set", if "pmpcfg_shift >= 32", "0xff << pmpcfg_shift"
      will go beyond "unsigned int" width. This patch tries to fix this issue.
      
      In function 'pmp_get':
      	cfgmask = (0xff << pmpcfg_shift);
      			-->
      	cfgmask = (0xffUL << pmpcfg_shift);
      In function 'pmp_set':
      	cfgmask = ~(0xff << pmpcfg_shift);
      			-->
      	cfgmask = ~(0xffUL << pmpcfg_shift);
      
      Signed-off-by: default avatarLiush <liush.damon@gmail.com>
      Reviewed-by: default avatarAnup Patel <anup.patel@wdc.com>
      9bd5f8f1
  3. Jun 19, 2020
  4. Jun 18, 2020
  5. Jun 17, 2020
    • Huaqi Fang's avatar
      platform: Update Nuclei ux600 platform support · 518e85cc
      Huaqi Fang authored
      
      
      Changes are made to support our FPGA evaluation board,
      it has DDR memory(0xA0000000-0xB0000000).
      
      * Adapt the config.mk to match FPGA evaluation board DDR memory address
      * Since the RISC-V CPU core frequency of FPGA might change, so we use the
        fixed TIMER frequency to measure the real CPU core frequency.
      * And the UART baudrate has to set to 57600bps for Nuclei FPGA evaluation
        board when CPU core frequency is about 8MHz, otherwise the UART input
        will not work correctly.
      
      Signed-off-by: default avatarHuaqi Fang <578567190@qq.com>
      Reviewed-by: default avatarAnup Patel <anup.patel@wdc.com>
      518e85cc
  6. Jun 15, 2020
    • Alexandre Ghiti's avatar
      platform/lib: Allow the OS to map the regions that are protected by PMP · 6966ad0a
      Alexandre Ghiti authored
      
      
      This is achieved by removing the 'no-map' property from the
      'reserved-memory' node when PMP is present, otherwise we keep it as it
      offers a small protection if the OS does not map this region at all.
      A new callback in platform_override is introduced and allows to fixup the
      device-tree. It is used here to override this new default behaviour on
      SiFive Fu540 platforms that has an erratum that prevents S-mode software
      to access a PMP protected region using 1GB page table mapping.
      
      If PMP is present, telling the OS not to map the reserved regions does not
      add much protection since it only avoids access to regions that are already
      protected by PMP. But by not allowing the OS to map those regions, it
      creates holes in the OS system memory map and prevents the use of
      hugepages which would generate, among other benefits, less TLB miss.
      
      Signed-off-by: default avatarAlexandre Ghiti <alex@ghiti.fr>
      Reviewed-by: default avatarAtish Patra <atish.patra@wdc.com>
      Reviewed-by: default avatarAnup Patel <anup.patel@wdc.com>
      6966ad0a
    • Anup Patel's avatar
      lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va() · e2c3f01a
      Anup Patel authored
      
      
      The arguments/parameters of __sbi_hfence_gvma_vmid_gpa() and
      __sbi_hfence_vvma_asid_va() functions are swapped so we fix it.
      
      Currently, we did not face any issues because QEMU does a full
      TLB flush for all HFENCE instructions.
      
      We also improve documentation of HFENCE.GVMA and HFENCE.VVMA
      instruction encoding.
      
      Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
      Reviewed-by: default avatarAtish Patra <atish.patra@wdc.com>
      e2c3f01a
  7. Jun 10, 2020
  8. Jun 08, 2020
  9. Jun 05, 2020
  10. May 23, 2020
  11. May 19, 2020
  12. May 18, 2020