This PR fixes an incorrect line for setting scaling_governer in
benchmarking tips.

In preparation for adding essentially the same visitor to StreamChecker,
this patch factors this visitor out to a common header.

I'll be the first to admit that the interface of these classes are not
terrific, but it rather tightly held back by its main technical debt,
which is NoStoreFuncVisitor, the main descendant of
NoStateChangeVisitor.

Change-Id: I99d73ccd93a18dd145bbbc83afadbb432dd42b90

And change the previous GetPtrField to only peek() the base pointer.
We can get rid of a whole bunch of DupPtr ops this way.

[LoongArch] Add a pass to rewrite rd to r0 for non-computational instrs whose return values are unused (#94590)

This patch adds a peephole pass `LoongArchDeadRegisterDefinitions`. It
rewrites `rd` to `r0` when `rd` is marked as dead. It may improve the
register allocation and reduce pipeline hazards on CPUs without register
renaming and OOO.

This allows the ReportError functor to hold move-only types.

Since the constructor of ContextEdge takes ContextIds by value, we
should move it to the corresponding member variable as suggested by
clang-tidy's performance-unnecessary-value-param.

While we are at it, this patch updates a couple of callers.  To avoid
the ambiguity in the evaluation order among the constructor arguments,
I'm calling computeAllocType before calling the constructor.

This reverts commit d843c02a.

The the function is doing two fairly different things, depending on how
it is called. While this allows for some code reuse, it also makes it
hard to override it correctly. Possibly for this reason
ValueObjectSynthetic overerides GetChildAtIndex instead, which forces it
to reimplement some of its functionality, most notably caching of
generated children.

Splitting this up makes it easier to move the caching to a common place
(and hopefully makes the code easier to follow in general).

gcc patch:
https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=1f2ca510065a2033bac408eb5a960ef0126f25cc

Handle lvalues pointing to declarations, unions and member pointers.

For patterns where there are multiple results apart from dpsInits, this
fails.
E.g.:
```
%13:2 = iree_codegen.ukernel.generic "iree_uk_unpack"
ins(%extracted_slice : tensor<?x1x16x16xf32>) outs(%11 :
tensor<?x?xf32>) ... -> tensor<?x?xf32>, i32
``` 
The above op has results apart from dpsInit and hence fails. The PR
assumes that the result has dpsInits followed by nonDpsInits.

The availability attributes are stored on the function declarations. The
code was looking for them in the function template declarations. This
resulted in spuriously diagnosing (non-strict) availablity issues in
contexts that are not available.

Co-authored-by: Gabor Horvath <gaborh@apple.com>

1. merge valid check
2. use range base loop

The test will generate an empty `regalloc-amdgpu.s` file in test, which
causes an unresolved test.

This pull request port `regallocfast` to new pass manager. It exposes
the parameter `filter` to handle different register classes for AMDGPU.
IIUC AMDGPU need to allocate different register classes separately so it
need implement its own `--<reg-class>-regalloc`. Now users can use e.g.
`-passe=regallocfast<filter=sgpr>` to allocate specific register class.
The command line option `--regalloc-npm` is still in work progress, plan
to reuse the syntax of passes, e.g. use
`--regalloc-npm=regallocfast<filter=sgpr>,greedy<filter=vgpr>` to
replace `--sgpr-regalloc` and `--vgpr-regalloc`.

Also, converted the R600 RUN lines from some tests into standalone tests.

Test CodeGen/AMDGPU/build_vector.ll has the lit patterns partially
hand-written and the rest auto-generated. It doesn't look good when
changes are required with future patches. Auto-generating the entire
pattern. Moved out the R600 test into build_vector-r600.ll.

This reverts commit 5c104879.

The ArmV7 bot is complaining the change breaks the alignment.

before:
```
*** Dumping AST Record Layout
         0 | class llvm::SUnit
         0 |   SDNode * Node
         8 |   MachineInstr * Instr
        16 |   SUnit * OrigNode
        24 |   const MCSchedClassDesc * SchedClass
        32 |   class llvm::SmallVector<class llvm::SDep, 4> Preds
        32 |     class llvm::SmallVectorImpl<class llvm::SDep> (base)
        32 |       class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
        32 |         class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
        32 |           class llvm::SmallVectorBase<uint32_t> (base)
        32 |             void * BeginX
        40 |             unsigned int Size
        44 |             unsigned int Capacity
        48 |     struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
        48 |       char[64] InlineElts
       112 |   class llvm::SmallVector<class llvm::SDep, 4> Succs
       112 |     class llvm::SmallVectorImpl<class llvm::SDep> (base)
       112 |       class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
       112 |         class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
       112 |           class llvm::SmallVectorBase<uint32_t> (base)
       112 |             void * BeginX
       120 |             unsigned int Size
       124 |             unsigned int Capacity
       128 |     struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
       128 |       char[64] InlineElts
       192 |   unsigned int NodeNum
       196 |   unsigned int NodeQueueId
       200 |   unsigned int NumPreds
       204 |   unsigned int NumSuccs
       208 |   unsigned int NumPredsLeft
       212 |   unsigned int NumSuccsLeft
       216 |   unsigned int WeakPredsLeft
       220 |   unsigned int WeakSuccsLeft
       224 |   unsigned short NumRegDefsLeft
       226 |   unsigned short Latency
   228:0-0 |   _Bool isVRegCycle
   228:1-1 |   _Bool isCall
   228:2-2 |   _Bool isCallOp
   228:3-3 |   _Bool isTwoAddress
   228:4-4 |   _Bool isCommutable
   228:5-5 |   _Bool hasPhysRegUses
   228:6-6 |   _Bool hasPhysRegDefs
   228:7-7 |   _Bool hasPhysRegClobbers
   229:0-0 |   _Bool isPending
   229:1-1 |   _Bool isAvailable
   229:2-2 |   _Bool isScheduled
   229:3-3 |   _Bool isScheduleHigh
   229:4-4 |   _Bool isScheduleLow
   229:5-5 |   _Bool isCloned
   229:6-6 |   _Bool isUnbuffered
   229:7-7 |   _Bool hasReservedResource
       232 |   Sched::Preference SchedulingPref
   236:0-0 |   _Bool isDepthCurrent
   236:1-1 |   _Bool isHeightCurrent
       240 |   unsigned int Depth
       244 |   unsigned int Height
       248 |   unsigned int TopReadyCycle
       252 |   unsigned int BotReadyCycle
       256 |   const TargetRegisterClass * CopyDstRC
       264 |   const TargetRegisterClass * CopySrcRC
           | [sizeof=272, dsize=272, align=8,
           |  nvsize=272, nvalign=8]
```

after:
```
*** Dumping AST Record Layout
         0 | class llvm::SUnit
         0 |   union llvm::SUnit::(anonymous at /Users/jonathan_roelofs/llvm-upstream/llvm/include/llvm/CodeGen/ScheduleDAG.h:246:5)
         0 |     SDNode * Node
         0 |     MachineInstr * Instr
         8 |   SUnit * OrigNode
        16 |   const MCSchedClassDesc * SchedClass
        24 |   const TargetRegisterClass * CopyDstRC
        32 |   const TargetRegisterClass * CopySrcRC
        40 |   class llvm::SmallVector<class llvm::SDep, 4> Preds
        40 |     class llvm::SmallVectorImpl<class llvm::SDep> (base)
        40 |       class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
        40 |         class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
        40 |           class llvm::SmallVectorBase<uint32_t> (base)
        40 |             void * BeginX
        48 |             unsigned int Size
        52 |             unsigned int Capacity
        56 |     struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
        56 |       char[64] InlineElts
       120 |   class llvm::SmallVector<class llvm::SDep, 4> Succs
       120 |     class llvm::SmallVectorImpl<class llvm::SDep> (base)
       120 |       class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
       120 |         class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
       120 |           class llvm::SmallVectorBase<uint32_t> (base)
       120 |             void * BeginX
       128 |             unsigned int Size
       132 |             unsigned int Capacity
       136 |     struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
       136 |       char[64] InlineElts
       200 |   unsigned int NodeNum
       204 |   unsigned int NodeQueueId
       208 |   unsigned int NumPreds
       212 |   unsigned int NumSuccs
       216 |   unsigned int NumPredsLeft
       220 |   unsigned int NumSuccsLeft
       224 |   unsigned int WeakPredsLeft
       228 |   unsigned int WeakSuccsLeft
       232 |   unsigned int TopReadyCycle
       236 |   unsigned int BotReadyCycle
       240 |   unsigned int Depth
       244 |   unsigned int Height
   248:0-0 |   _Bool isVRegCycle
   248:1-1 |   _Bool isCall
   248:2-2 |   _Bool isCallOp
   248:3-3 |   _Bool isTwoAddress
   248:4-4 |   _Bool isCommutable
   248:5-5 |   _Bool hasPhysRegUses
   248:6-6 |   _Bool hasPhysRegDefs
   248:7-7 |   _Bool hasPhysRegClobbers
   249:0-0 |   _Bool isPending
   249:1-1 |   _Bool isAvailable
   249:2-2 |   _Bool isScheduled
   249:3-3 |   _Bool isScheduleHigh
   249:4-4 |   _Bool isScheduleLow
   249:5-5 |   _Bool isCloned
   249:6-6 |   _Bool isUnbuffered
   249:7-7 |   _Bool hasReservedResource
       250 |   unsigned short NumRegDefsLeft
       252 |   unsigned short Latency
   254:0-0 |   _Bool isDepthCurrent
   254:1-1 |   _Bool isHeightCurrent
   254:2-2 |   _Bool isNode
   254:3-3 |   _Bool isInst
   254:4-7 |   Sched::Preference SchedulingPref
           | [sizeof=256, dsize=255, align=8,
           |  nvsize=255, nvalign=8]
```

Following of https://github.com/llvm/llvm-project/pull/86912

The motivation of the patch series is that, for a module interface unit
`X`, when the dependent modules of `X` changes, if the changes is not
relevant with `X`, we hope the BMI of `X` won't change. For the specific
patch, we hope if the changes was about irrelevant declaration changes,
we hope the BMI of `X` won't change. **However**, I found the patch
itself is not very useful in practice, since the adding or removing
declarations, will change the state of identifiers and types in most
cases.

That said, for the most simple example,

```
// partA.cppm
export module m:partA;

// partA.v1.cppm
export module m:partA;
export void a() {}

// partB.cppm
export module m:partB;
export void b() {}

// m.cppm
export module m;
export import :partA;
export import :partB;

// onlyUseB;
export module onlyUseB;
import m;
export inline void onluUseB() {
    b();
}
```

the BMI of `onlyUseB` will change after we change the implementation of
`partA.cppm` to `partA.v1.cppm`. Since `partA.v1.cppm` introduces new
identifiers and types (the function prototype).

So in this patch, we have to write the tests as:

```
// partA.cppm
export module m:partA;
export int getA() { ... }
export int getA2(int) { ... }

// partA.v1.cppm
export module m:partA;
export int getA() { ... }
export int getA(int) { ... }
export int getA2(int) { ... }

// partB.cppm
export module m:partB;
export void b() {}

// m.cppm
export module m;
export import :partA;
export import :partB;

// onlyUseB;
export module onlyUseB;
import m;
export inline void onluUseB() {
    b();
}
```

so that the new introduced declaration `int getA(int)` doesn't introduce
new identifiers and types, then the BMI of `onlyUseB` can keep
unchanged.

While it looks not so great, the patch should be the base of the patch
to erase the transitive change for identifiers and types since I don't
know how can we introduce new types and identifiers without introducing
new declarations. Given how tightly the relationship between
declarations, types and identifiers, I think we can only reach the ideal
state after we made the series for all of the three entties.

The design of the patch is similar to
https://github.com/llvm/llvm-project/pull/86912, which extends the
32-bit DeclID to 64-bit and use the higher bits to store the module file
index and the lower bits to store the Local Decl ID.

A slight difference is that we only use 48 bits to store the new DeclID
since we try to use the higher 16 bits to store the module ID in the
prefix of Decl class. Previously, we use 32 bits to store the module ID
and 32 bits to store the DeclID. I don't want to allocate additional
space so I tried to make the additional space the same as 64 bits. An
potential interesting thing here is about the relationship between the
module ID and the module file index. I feel we can get the module file
index by the module ID. But I didn't prove it or implement it. Since I
want to make the patch itself as small as possible. We can make it in
the future if we want.

Another change in the patch is the new concept Decl Index, which means
the index of the very big array `DeclsLoaded` in ASTReader. Previously,
the index of a loaded declaration is simply the Decl ID minus
PREDEFINED_DECL_NUMs. So there are some places they got used
ambiguously. But this patch tried to split these two concepts.

As https://github.com/llvm/llvm-project/pull/86912 did, the change will
increase the on-disk PCM file sizes. As the declaration ID may be the
most IDs in the PCM file, this can have the biggest impact on the size.
In my experiments, this change will bring 6.6% increase of the on-disk
PCM size. No compile-time performance regression observed. Given the
benefits in the motivation example, I think the cost is worthwhile.

Short-circuit the parsing of tok::colon to label colons found within
lines starting with asm as InlineASMColon.

Fixes #92616.

---------

Co-authored-by: Owen Pan <owenpiano@gmail.com>

Instead of having multiple places insert into the Features vector
independently, check all the conditions in one place.

This avoids a subtle ordering requirement that -mstrict-align processing
had to be done after the others.

We don't need the `noundef` check if the new simplification is a
constant.

This cleans up regressions from folding multiuse:
    `(icmp eq/ne (sub/xor x, y), 0)` -> `(icmp eq/ne x, y)`.

Closes #88298

Make it easier to add CREL support.

This test case shows a limitation of DFSan's sscanf implementation
(introduced in https://reviews.llvm.org/D153775): it simply ignores
ordinary characters in the format string, instead of actually comparing
them against the input. This may change the semantics of instrumented
programs.

Importantly, this also means that DFSan's release_shadow_space.c test,
which relies on sscanf to scrape the RSS from /proc/maps output, will
incorrectly match lines that don't contain RSS information. As a result,
it adding together numbers from irrelevant output (e.g., base
addresses), resulting in test flakiness
(https://github.com/llvm/llvm-project/issues/91287).

Fixes #94555.