[llvm][ScheduleDAG] Re-arrange SUnit's members to make it smaller (#94547)

before:
```
*** Dumping AST Record Layout
         0 | class llvm::SUnit
         0 |   SDNode * Node
         8 |   MachineInstr * Instr
        16 |   SUnit * OrigNode
        24 |   const MCSchedClassDesc * SchedClass
        32 |   class llvm::SmallVector<class llvm::SDep, 4> Preds
        32 |     class llvm::SmallVectorImpl<class llvm::SDep> (base)
        32 |       class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
        32 |         class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
        32 |           class llvm::SmallVectorBase<uint32_t> (base)
        32 |             void * BeginX
        40 |             unsigned int Size
        44 |             unsigned int Capacity
        48 |     struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
        48 |       char[64] InlineElts
       112 |   class llvm::SmallVector<class llvm::SDep, 4> Succs
       112 |     class llvm::SmallVectorImpl<class llvm::SDep> (base)
       112 |       class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
       112 |         class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
       112 |           class llvm::SmallVectorBase<uint32_t> (base)
       112 |             void * BeginX
       120 |             unsigned int Size
       124 |             unsigned int Capacity
       128 |     struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
       128 |       char[64] InlineElts
       192 |   unsigned int NodeNum
       196 |   unsigned int NodeQueueId
       200 |   unsigned int NumPreds
       204 |   unsigned int NumSuccs
       208 |   unsigned int NumPredsLeft
       212 |   unsigned int NumSuccsLeft
       216 |   unsigned int WeakPredsLeft
       220 |   unsigned int WeakSuccsLeft
       224 |   unsigned short NumRegDefsLeft
       226 |   unsigned short Latency
   228:0-0 |   _Bool isVRegCycle
   228:1-1 |   _Bool isCall
   228:2-2 |   _Bool isCallOp
   228:3-3 |   _Bool isTwoAddress
   228:4-4 |   _Bool isCommutable
   228:5-5 |   _Bool hasPhysRegUses
   228:6-6 |   _Bool hasPhysRegDefs
   228:7-7 |   _Bool hasPhysRegClobbers
   229:0-0 |   _Bool isPending
   229:1-1 |   _Bool isAvailable
   229:2-2 |   _Bool isScheduled
   229:3-3 |   _Bool isScheduleHigh
   229:4-4 |   _Bool isScheduleLow
   229:5-5 |   _Bool isCloned
   229:6-6 |   _Bool isUnbuffered
   229:7-7 |   _Bool hasReservedResource
       232 |   Sched::Preference SchedulingPref
   236:0-0 |   _Bool isDepthCurrent
   236:1-1 |   _Bool isHeightCurrent
       240 |   unsigned int Depth
       244 |   unsigned int Height
       248 |   unsigned int TopReadyCycle
       252 |   unsigned int BotReadyCycle
       256 |   const TargetRegisterClass * CopyDstRC
       264 |   const TargetRegisterClass * CopySrcRC
           | [sizeof=272, dsize=272, align=8,
           |  nvsize=272, nvalign=8]
```

after:
```
*** Dumping AST Record Layout
         0 | class llvm::SUnit
         0 |   union llvm::SUnit::(anonymous at /Users/jonathan_roelofs/llvm-upstream/llvm/include/llvm/CodeGen/ScheduleDAG.h:246:5)
         0 |     SDNode * Node
         0 |     MachineInstr * Instr
         8 |   SUnit * OrigNode
        16 |   const MCSchedClassDesc * SchedClass
        24 |   const TargetRegisterClass * CopyDstRC
        32 |   const TargetRegisterClass * CopySrcRC
        40 |   class llvm::SmallVector<class llvm::SDep, 4> Preds
        40 |     class llvm::SmallVectorImpl<class llvm::SDep> (base)
        40 |       class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
        40 |         class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
        40 |           class llvm::SmallVectorBase<uint32_t> (base)
        40 |             void * BeginX
        48 |             unsigned int Size
        52 |             unsigned int Capacity
        56 |     struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
        56 |       char[64] InlineElts
       120 |   class llvm::SmallVector<class llvm::SDep, 4> Succs
       120 |     class llvm::SmallVectorImpl<class llvm::SDep> (base)
       120 |       class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
       120 |         class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
       120 |           class llvm::SmallVectorBase<uint32_t> (base)
       120 |             void * BeginX
       128 |             unsigned int Size
       132 |             unsigned int Capacity
       136 |     struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
       136 |       char[64] InlineElts
       200 |   unsigned int NodeNum
       204 |   unsigned int NodeQueueId
       208 |   unsigned int NumPreds
       212 |   unsigned int NumSuccs
       216 |   unsigned int NumPredsLeft
       220 |   unsigned int NumSuccsLeft
       224 |   unsigned int WeakPredsLeft
       228 |   unsigned int WeakSuccsLeft
       232 |   unsigned int TopReadyCycle
       236 |   unsigned int BotReadyCycle
       240 |   unsigned int Depth
       244 |   unsigned int Height
   248:0-0 |   _Bool isVRegCycle
   248:1-1 |   _Bool isCall
   248:2-2 |   _Bool isCallOp
   248:3-3 |   _Bool isTwoAddress
   248:4-4 |   _Bool isCommutable
   248:5-5 |   _Bool hasPhysRegUses
   248:6-6 |   _Bool hasPhysRegDefs
   248:7-7 |   _Bool hasPhysRegClobbers
   249:0-0 |   _Bool isPending
   249:1-1 |   _Bool isAvailable
   249:2-2 |   _Bool isScheduled
   249:3-3 |   _Bool isScheduleHigh
   249:4-4 |   _Bool isScheduleLow
   249:5-5 |   _Bool isCloned
   249:6-6 |   _Bool isUnbuffered
   249:7-7 |   _Bool hasReservedResource
       250 |   unsigned short NumRegDefsLeft
       252 |   unsigned short Latency
   254:0-0 |   _Bool isDepthCurrent
   254:1-1 |   _Bool isHeightCurrent
   254:2-2 |   _Bool isNode
   254:3-3 |   _Bool isInst
   254:4-7 |   Sched::Preference SchedulingPref
           | [sizeof=256, dsize=255, align=8,
           |  nvsize=255, nvalign=8]
```