This can happen when an initializer returns a dummy pointer.

This is currently NFC but required for later changes. A Ret op
might fail and set the result to invalid, causing another setInvalid()
call, which asserts that the result is still empty.

We are replacing a narrow IV increment with a wider one. If the original
(narrow) increment did not wrap, the wider one should not wrap either.
Set the flags to be the union of both wide increment and original
increment; this ensures we preserve flags SCEV could infer for the wider
increment.

Fixes https://github.com/llvm/llvm-project/issues/71517.

Similar to D110763.

We were unnecessarily getting the pointer of the local variable twice.

Having the test in the header requires including unistd.h on POSIX
platforms. This header has other declarations which may conflict with
code that uses named declarations provided by this header. For example
code using "int pipe;" would conflict with the function pipe in this
header.

Moving the code to the dylib means std::print would not be available on
Apple backdeployment targets. On POSIX platforms there is no transcoding
required so a not Standard conforming implementation is still a useful
and the observable differences are minimal. This behaviour has been done
for print before https://github.com/llvm/llvm-project/pull/76293.

Note questions have been raised in LWG4044 "Confusing requirements for
std::print on POSIX platforms", whether or not the isatty check on POSIX
platforms is required. When this LWG issue is resolved the
backdeployment targets could become Standard compliant.

This patch is intended to be backported to the LLVM-18 branch.

Fixes: https://github.com/llvm/llvm-project/issues/79782

[Flang] Support passing a function that returns procedure pointer as actual corresponding to a procedure dummy. (#80891)

Flang crashes with the following case. The problem is we missed the case
when passing a reference to a function that returns a procedure pointer
as actual that corresponds to a procedure dummy. This PR is to fix that.

```
  PROGRAM main
  IMPLICIT NONE
  INTERFACE
    FUNCTION IntF(Arg)
      integer :: Arg, IntF
    END FUNCTION
  END INTERFACE

  INTERFACE
    FUNCTION RetPtr(Arg)
      IMPORT
      PROCEDURE(IntF) :: Arg
      PROCEDURE(IntF), POINTER :: RetPtr
    END FUNCTION
  END INTERFACE

  CALL ModSub(RetPtr(IntF))
  contains
    SUBROUTINE ModSub(Fun1)
    PROCEDURE(IntF) :: Fun1
    END SUBROUTINE
  END
  ```

After applying the review comments of
https://github.com/llvm/llvm-project/pull/80478
I've forgotten to update the generated files. This fixes the issue and
removes trailing whitespace.

-DLIBCXX_ENABLE_UNICODE=OFF or -D_LIBCPP_HAS_NO_UNICODE doesn't build
without this change.

This patch enable hardware shadow stack with `Zicifss` and
`mno-forced-sw-shadow-stack`. New feature forced-sw-shadow-stack
disables hardware shadow stack even when `Zicfiss` enabled.

Applies LWG3050 to the constraints of operator*, operator/, and
operator%. The changes to the constructor were done in
https://reviews.llvm.org/D118902

, but that patch did not identify the
related LWG-issue, and only adjusted the constructor to the wording in
the Standard.

Implements:
- LWG 3050: Conversion specification problem in chrono::duration
constructor

---------

Co-authored-by: h-vetinari <h.vetinari@gmx.com>

ARM64EC import libraries expose two additional symbols: mangled thunk
symbol (like `#func`) and auxiliary import symbol (like`__imp_aux_func`).
The main functional change with this patch is that those symbols are
properly added to static library ECSYMBOLS.

This reverts commit bb5c3899.

That commit caused failed asserts like this:

$ cat repro.c
float a, b;
double sqrt();
void c() { b = a / sqrt(a); }
$ clang -target x86_64-linux-gnu -c -O2 -ffast-math repro.c
clang: ../lib/IR/Instruction.cpp:522: bool llvm::Instruction::hasAllowReassoc() const: Assertion `isa<FPMathOperator>(this) && "getting fast-math flag on invalid op"' failed.

Add a pass to convert jump tables to switches.
The new pass replaces an indirect call with a switch + direct calls if all the functions in the jump table are smaller than the provided threshold.
The pass is currently disabled by default and can be enabled by -enable-jump-table-to-switch.

Test plan: ninja check-all

I was looking through to check whether Nan was being handled correctly,
and couldn't work out why simple cases were behaving differently than
they should. It turns out the initial limit values was backwards for
minloc/maxloc reductions in general. This fixes that, introduced in
#79469.

I don't think the transient alignment needs to be larger than the
ABI alignment.

We apply custom lowering to 64 bit constants where we use the same logic
as in non-global isel: if materializing in registers is too expensive,
we emit a load from constant pool. Later, during instruction selection,
constant pool address is generated using `selectAddr`.

This makes it easier to run the tests in a containerized environment.

Drop the "Always" prefix to remove the self-contradiction.

… inside modules (#81087)"

This reverts commit 0802596d.

See comments in PR #81087 for a test case that shows why I'm reverting.

Make the type match the printf format.

…fatal error report

This makes the behavior of HWASan matching with ASan: always call user
provided callback function for an error report, but only call
`SetAbortMessage()` on Android when `flags()->halt_on_error` is true.

It claimed to dump all sections by default, but this hasn't been true
since 2017: https://reviews.llvm.org/D37717

EXPORTAS is a new name type in import libraries. It's used by default on ARM64EC,
but it's allowed on other platforms as well.

This reverts commit 01440115.

This PR adds a new attribute to represent the CUDA attribute attached to
procedure. This attribute is attached to the func.func operation during
lowering.
Other procedures information such as `launch_bounds` and `cluster_dims`
will be added separately.

The Ampere1B core is enabled with a new scheduling/pipeline model, as it
provides significant updates over the Ampere1 core; it reduces latencies
on many instructions, has some micro-ops reassigned between the XY and X
units, and provides modelling for the instructions added since Ampere1
and Ampere1A.

Both Ampere1 and Ampere1A support fusion of ADRP+ADD.
This adds the missing feature to enable fusion-aware scheduling for this
case.

Ampere1A introduced the Fusion for A+B+1/A-B-1.
However, the Feature flag to enable that fusion-case never was added to
TuneAmpere1A.  This commit corrects that omission.

The Ampere1B is Ampere's third-generation core implementing a
superscalar, out-of-order microarchitecture with nested virtualization,
speculative side-channel mitigation and architectural support for
defense against ROP/JOP style software attacks.

Ampere1B is an ARMv8.7+ implementation, adding support for the FEAT
WFxT, FEAT CSSC, FEAT PAN3 and FEAT AFP extensions. It also includes all
features of the second-generation Ampere1A, such as the Memory Tagging
Extension and SM3/SM4 cryptography instructions.

Since we commit all changes to the release branch CI to main first, we
need someway to test that these changes to main don't break the CI.