Given a list of constraints for InlineAsm (ex. "imr") I'm looking to
modify the order in which they are chosen. Before doing so, I noticed a
fair
amount of logic is duplicated between SelectionDAGISel and GlobalISel
for this.

That is because SelectionDAGISel is also trying to lower immediates
during selection. If we detangle these concerns into:
1. choose the preferred constraint
2. attempt to lower that constraint

Then we can slide down the list of constraints until we find one that
can be lowered. That allows the implementation to be shared between
instruction selection frameworks.

This makes it so that later I might only need to adjust the priority of
constraints in one place, and have both selectors behave the same.

Reviewed By: Joe_Nash

Differential Revision: https://reviews.llvm.org/D156103

I was trying to run the tests on FreeBSD and noticed that we weren't
printing symbol names. It turns out this is because of the missing
-Wl,--export-dynamic flag. Instead of hardcoding the name of the flag
and only passing it for Linux hosts, use a pre-existing CMake variable
instead. I was not aware of this flag, but it appears to have been
supported for the past 16 years (with support for more platforms added
later):
https://gitlab.kitware.com/cmake/cmake/-/commit/66d1930f5674f08e09f455b3f0777f2de3e0717e

It was already removed once in D19265, but was reintroduced in D20353.

After landing the implementation of LWG3545, I realized that the tests
for std::pointer_traits had become a bit disorganized. This patch is a
NFC that refactors the tests:
- Move compile-only tests to `.compile.pass.cpp` tests
- Re-create the clear distinction between tests for the std::pointer_traits base tempate and for the T* specialization.
- De-duplicate test coverage -- we had a bunch of things that were tested in duplication.

If LMUL is more than m1, we can be more aggressive about narrowing the
build_vector via a vsext if legal. If the narrow build_vector gets
lowered as a load, while both are linear in lmul, load uops are
generally more expensive than extend uops. If the narrow build_vector
gets lowered via dominant values, that work is linear in both #unique
elements and LMUL. So provided the number of unique values > 2, this is
a net win in work performed.

In the new syntax, we will parse **loose_compressed** as
**CompressedWithHigh** and **block2_4** as **TwoOutOfFour** level
format. Currently, we support unique and order as level properties.

This reverts commit 390ac823.

It broke the sphinx publish bots for our documentation:
https://lab.llvm.org/buildbot/#/builders/242/builds/1130

because that machine has GCC 9.4.0 which does not know about C++23

/llvm-project/mlir/include/mlir/Dialect/Transform/IR/TransformInterfaces.h:235:12: error: unused variable 'sameTimestamp' [-Werror,-Wunused-variable]
      bool sameTimestamp =
           ^
/llvm-project/mlir/include/mlir/Dialect/Transform/IR/TransformInterfaces.h:260:12: error: unused variable 'sameTimestamp' [-Werror,-Wunused-variable]
      bool sameTimestamp =
           ^
2 errors generated.

This patch implements the `getCalleeSavedRegs` function for AArch64,
addressing the issue where the "not implemented" error occurs when
both the `--assume-abi` option and options related to the
RegAnalysis Pass (e.g., `--indirect-call-promotion=all`) are enabled.

This allows running tests like the ones for std::cin even on SSH
executors. This was originally reported as
https://github.com/llvm/llvm-project/pull/66842#issuecomment-1728701639.

AppleClang 15 was released on September 18th and is now stable. Per our
policy, we're bumping the supported AppleClang compiler to the latest
release. This allows cleaning up the test suite, but most importantly
unblocking various other patches that are blocked on bumping the
compiler requirements.

FreeBSD does not support riscv32 and has no intention of doing so.

Same as #66369 but for payload values. (#66369 added checks only for
payload operations.)

It was necessary to change the signature of `getPayloadValues` to return
an iterator. This is now similar to payload operations.

Fixes an issue in #66369 where the `LLVM_ENABLE_ABI_BREAKING_CHECKS`
check was inverted.

The implementation doesn't emit any diagnostics as it is shared with the
pattern-based implementation. Check preconditions early and emit
diagnostics from the transform op instead. Without this change, the op
would produce a definite failure and no error message.

This patch adds a LLVM_FORCE_VC_REVISION option to force a custom
VC revision to be included instead of trying to fetch one from a
git command. This is helpful in environments where git is not
available or is non-functional but the vc revision is available
through some other means.

The vscale_range is used for scalabale vector functionality in Arm
Scalable Vector Extension to select the size of vector operation (and I
thnk RISCV has something similar).

This patch adds the base support for the vscale_range attribute to the
LLVM::FuncOp, and the marshalling for translation to LLVM-IR and import
from LLVM-IR to LLVM dialect.

This attribute is intended to be used at higher level MLIR, specified
either by command-line options to the compiler or using compiler
directives (e.g. pragmas or function attributes in the source code) to
indicate the desired range.

To help future contributors understand a couple of mysterious
out-of-bound tests, add a brief comment to each.

Vector constants are always lowered via constant pool loads. This patch selects
MOVI/MVNI in more cases where appropriate.

This patch updates the mask creation code to always create compares of
the form (ICMP_ULE, wide canonical IV, backedge-taken-count) up front
when tail folding and introduce active-lane-mask as later
transformation.

This effectively makes (ICMP_ULE, wide canonical IV, backedge-taken-count)
the canonical form for tail-folding early on. Introducing more specific
active-lane-mask recipes is treated as a VPlan-to-VPlan optimization.

This has the advantage of keeping the logic  (and complexity) of
introducing active-lane-mask recipes in a single place, instead of
spreading the logic out across multiple functions. It also simplifies
initial VPlan construction and enables treating introducing EVL as
similar optimization.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D158779

The most straightforward extension to D150851 would involve handling the
decreasing IV case, for which tests have been added in 110ec186
(LoopVectorize/iv-select-cmp: add test for decreasing IV, const start).
However, the commit missed a testcase for the out-of-bound sentinel
value LONG_MAX, which should not be vectorized. Fix this by adding a
test corresponding to the following program:

  long test(long *a) {
    long rdx = 331;
    for (long i = LONG_MAX; i >= 0; i--) {
      if (a[i] > 3)
        rdx = i;
    }
    return rdx;
  }

Differential Revision: https://reviews.llvm.org/D157969

Recommonmark has been deprecated, then archived last year. This was
tracked by: https://github.com/llvm/llvm-iwg/issues/30

See https://github.com/readthedocs/recommonmark

This patch migrates all our doc to use myst

Additional details for bot maintainers: https://discourse.llvm.org/t/maintenance-required-on-sphinx-build-bots/73612

This PR extends the error message of the tracking listener when
replacement ops cannot be found. That may happen if the applied patterns
replace an op by an op of a different kind or by block arguments.
However, this only matters if there are alive handles to the replaced
op. The new error message mentions that explicitly and reports the alive
handles.

This reverts commit a0460399 because
it broke the OpenMP buildbot.

Support all known permutations when lowering masked vector.contract to
vector.outerproduct, and not just the canonical permutation.

We used to return `int` in `getAsInt`, while `IntInit::getValue`
returns `int64_t` and `utohexstr` needs `uint64_t`. The casting
causes the wrong hex value when printing bits value.

Teach the si-fix-sgpr-copies pass to deal with REG_SEQUENCE, PHI or
INSERT_SUBREG where the result is an SGPR, but some of the inputs are
constants materialized into VGPRs. This may happen in cases where for
instance several instructions use an immediate zero and SelectionDAG
chooses to put it in a VGPR to satisfy all of them. This however causes
the si-fix-sgpr-copies to try to switch the whole chain to VGPR and may
lead to illegal VGPR-to-SGPR copies. Rematerializing the constant into
an SGPR fixes the issue.

This helps to slightly simplify code when a recipe can be obtained
easily. Suggested in D158779.

This patch adds support for lowering vector.transpose to ArmSME. It's
implemented by storing the input tile of the tranpose to memory and
reloading vertically, building on top of the tile slice layout support.

Tranposing via memory is obviously expensive, the current intention is
to avoid the transpose if possible, this is therefore intended as a
fallback and to provide base support for Vector ops. If it turns out
transposes can't be avoided then this should be replaced with a more
optimal implementation, perhaps with tile <-> vector (MOVA) ops.

Depends on https://github.com/llvm/llvm-project/pull/66758.

By ensuring the base is only visited once. This avoids infinite
recursion and expontential running times in some corner cases.

See the added tests for examples.

Apart from the cases that caused infinite recursion and used to crash,
this change is an NFC and results of the matchers are the same.

This is part of the efforts adding .gnu_attribute support for PowerPC.
In Clang, an extra metadata field will be added as float-abi to show
current long double format. So backend can emit .gnu_attribute section
data from this metadata.

To avoid breaking existing behavior, the module metadata will only be
emitted when this module makes use of long double.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D116016

[MachineSink][AArch64] Sink instruction copies when they can replace copy into hard register or folded into addressing mode

This patch adds a new code transformation to the `MachineSink` pass,
that tries to sink copies of an instruction, when the copies can be folded
into the addressing modes of load/store instructions, or
replace another instruction (currently, copies into a hard register).

The criteria for performing the transformation is that:
* the register pressure at the sink destination block must not
  exceed the register pressure limits
* the latency and throughput of the load/store or the copy must not deteriorate
* the original instruction must be deleted

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D152828

The documentation for how to use "gh pr merge" was broken.
In one place it said '--delete-branch' (which seem to be correct for
that option). But in second place it said '--delete branch' and in a
third place it just said '--delete'.
Make sure '--delete-branch' is used in all three places.

This patch implements getCFInstrCost TTI hook that mostly affects
LoopVectorizer decisions. It sets zero cost for PHI nodes and zero
throughput cost for branches (assuming that branches are likely to
be predicted). The implementation is similar to X86/AArch64/PowerPC
targets and reduces loop cost by excluding induction PHIs/loop latch
branches, which in turn leads to selecting smaller vectorization
factor.