https://reviews.llvm.org/D123498 contains a few errors resulting in incorrect target contents or mismatched target/list names. This patch fixes all the known errors.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D126002

This brings the MachineInstrs in line with the corresponding intrinsics
which have side effects but do not access memory. It also matches how
BUF cache invalidation instructions are defined.

The lit test changes are just because the machine scheduler previously
treated them like loads, and added an artificial scheduling edge from
them to the exit SU, which caused them to be scheduled earlier.

Differential Revision: https://reviews.llvm.org/D126074

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D126039

Previously, clangd would filter completions only on the first part of
the selector (first typed chunk) instead of all remaining selector
fragments (all typed chunks).

Differential Revision: https://reviews.llvm.org/D124637

This changes adds the option to lower to NvGpu dialect ops during the
VectorToGPU convsersion pass. Because this transformation reuses
existing VectorToGPU logic, a seperate VectorToNvGpu conversion pass is
not created. The option `use-nvgpu` is added to the VectorToGPU pass.
When this is true, the pass will attempt to convert slices rooted at
`vector.contract` operations into `nvgpu.mma.sync` ops, and
`vector.transfer_read` ops are converted to either `nvgpu.ldmatrix` or
one or more `vector.load` operations.  The specific data loaded will
depend on the thread id within a subgroup (warp). These index
calculations depend on data type and shape of the MMA op
according to the downstream PTX specification. The code for supporting
these details is separated into `NvGpuSupport.cpp|h`.

Differential Revision: https://reviews.llvm.org/D122940

Differential revision: https://reviews.llvm.org/D125658

Introduces basic test coverage for frem on x86.

Split off from https://reviews.llvm.org/D125988

Differential Revision: https://reviews.llvm.org/D126055

Disable scripted_crashlog_json.test on Apple Silicon until Ismail has
bandwidth to investigate.

rdar://93655633

Extend SIInstrInfo::isOperandLegal to enforce a limit on the number of
literal operands for all VALU instructions, not just VOP3. In particular
it now handles VOP2 instructions with a mandatory literal operand like
V_FMAAK_F32.

Differential Revision: https://reviews.llvm.org/D126064

Extend the literal operand checking in SIInstrInfo::verifyInstruction to
check VOP2 instructions like V_FMAAK_F32 which have a mandatory literal
operand. The rule is that src0 can also be a literal, but only if it is
the same literal value.

AMDGPUAsmParser::validateConstantBusLimitations already handles this
correctly.

Differential Revision: https://reviews.llvm.org/D126063

Reviewed By: ldionne, #libc

Spies: jwakely, rodgert, libcxx-commits

Differential Revision: https://reviews.llvm.org/D125634

This reverts commit 94d6dd90.

LSP supports Diagnostic.codeInformation since 3.16.
In VSCode, this turns the code (e.g. "unused-includes" or "bugprone-foo") into
a clickable link that opens the docs in a web browser.

Differential Revision: https://reviews.llvm.org/D126065

We have autogenerated pragma regions in our code
which where awkwardly broken up like this:

```
#pragma region foo(bar : hello)
```
becomes

```
#pragma region foo(bar \
                   : hello)
```

This fixes the problem by adding region as a keyword
and handling it the same way as pragma mark

Reviewed By: curdeius

Differential Revision: https://reviews.llvm.org/D125961

Reviewed By: martong

Differential Revision: https://reviews.llvm.org/D125920

Support for `__attribute__((no_builtin("foo")))` was added in https://reviews.llvm.org/D68028,
but builtins were still being used even when the attribute was placed on a function.

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D124701

We should not surface CMake-level options like LIBCXX_ENABLE_FILESYSTEM
to our users, since they don't know what it means. Instead, use a slightly
more general wording.

Also, add an error in <ios> to improve the quality of errors for people
trying to use <iostream> when localization is disabled.

Differential Revision: https://reviews.llvm.org/D125910

Differential Revision: https://reviews.llvm.org/D125981

32 Bit windows includes attribute 'thiscall' on member functions as a
default calling convention.  This test was not written in a way that
works with that, so added wildcards so it is tolerant of it.

This used to be D102158, but all the code it describes got re-written, so I
figured I'd take another shot at documenting the new instruction referencing
variable locations, this time from a higher level. Happily there's no longer any
need to describe LiveDebugValues in any detail seeing how it's all SSA-based
now.

Probably the most important part is the explanation of what targets need to do
to support instruction referencing. The list is small, mostly because there's
nothing especially complicated that targets need to do: just instrument their
target-specific optimisations and implement the stack spill/restore recognition
target hooks.

This is a small amount of text (which is a virtue), I'm extremely happy to
expand on anything.

Differential Revision: https://reviews.llvm.org/D113586



Co-authored-by: Jeremy Morse <jeremy.morse@sony.com>

This was shown as a potential regression in D126040.

While here, update the auto-generated checks to also check
the match the function parameters - there was a potential
miscompile that would go unnoticed with the more lenient
check lines.

SLP vectorizer emits extracts for externally used vectorized scalars and
estimates the cost for each such extract. But in many cases these
scalars are input for insertelement instructions, forming buildvector,
and instead of extractelement/insertelement pair we can emit/cost
estimate shuffle(s) cost and generate series of shuffles, which can be
further optimized.

Tested using test-suite (+SPEC2017), the tests passed, SLP was able to
generate/vectorize more instructions in many cases and it allowed to reduce
number of re-vectorization attempts (where we could try to vectorize
buildector insertelements again and again).

Differential Revision: https://reviews.llvm.org/D107966

to make features like hover, go-to-def work when the cursor is on the
UnresolvedUsingTypeLoc.

Differential Revision: https://reviews.llvm.org/D125684

This patch implements a for a target specific optimization that replaces
the cmp and csel from cttz with an and mask.

Recommitted with a fix for truncated value sizes.

Differential Revision: https://reviews.llvm.org/D123782

We must add padding when using SP or BP to access stack objects.
Checking whether we're missing FP is not sufficient as stack realignment
uses SP too. The test in D125962 explains the specific issue in more
detail.

Split from D125787.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D125964

This test (and its forthcoming fix) was split off from D125787. It shows
that the logic we use to determine when we need to add extra RVV padding
is insufficient.

In this example, we may have a situation involving dynamic stack
alignment -- but no variable-sized objects -- where we have no FP but
must still use SP to index objects. In this case we also need the
extra RVV padding, otherwise objects may overlap. Specifically, the test
shows that the RVV vector object may clobber the lowest callee-save.

    |------------------------------| -- <-- Incoming SP
    | 4-byte callee-save (ra)      |
    |------------------------------| -- <-- SP + VLENB*2 + 60
    | 4-byte callee-save (s0)      |
    |------------------------------| -- <-- SP + VLENB*2 + 56  --
    | 4-byte callee-save (s9)      |                            |
    |------------------------------| -- <-- SP + VLENB*2 + 52   | RVV object(!!)
    | VLENB*2 RVV object           |                            |
    |------------------------------| -- <-- SP + 56            --
    | 4-byte local object          |
    |------------------------------| -- <-- SP + 32
    | Dead area                    |
    |------------------------------| -- <-- InSP - 2*VLENB - 64
    | Possibly-zero realignment    |
    |------------------------------| -- <-- SP (realigned to 32)

This diagram should help show that when SP==InSP -- e.g., when the incoming SP
is 32-byte aligned, subtracting 2*VLENB+64 may keep it that way -- the RVV
object clobbers the spill of s9.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D125962

Add a set of tests that iterate over possible combinations of
memory orders for lock free stack implementation.

Reviewed By: dvyukov

Differential Revision: https://reviews.llvm.org/D110552

Change static function to X86LowerAMXCast member function.

Differential Revision: https://reviews.llvm.org/D126058

Differential Revision: https://reviews.llvm.org/D125907

For the hypothetical "a.b.c" op printed within a region that declares "a" as
the default dialect, MLIR would currently elide the "a." prefix and only print
"b.c". However, this becomes ambiguous while parsing as "b.c" may be exist as
the "c" op in the "b" dialect. If it does not, the parsing currently fails. Do
not elide the default dialect if the op name contains further dots to avoid the
ambiguity.

See https://discourse.llvm.org/t/dropping-dialect-prefix-for-ops-with-multiple-dots-in-the-name/62562

Reviewed By: rriddle

Differential Revision: https://reviews.llvm.org/D125975

Building on top of D125665, this adds MVE costs for fptosi.sat and
fptoui.sat, providing MVE is available and the types are legal.

Differential Revision: https://reviews.llvm.org/D125666