1. Aug 05, 2020
  2. Aug 01, 2020
  3. Jul 31, 2020
  4. Jul 30, 2020
  5. Jul 21, 2020
  6. Jul 18, 2020
  7. Jul 17, 2020
    • Schuyler Eldridge's avatar
      Merge pull request #1770 from freechipsproject/mergify/bp/1.3.x/pr-1753 · d56cecd8
      Schuyler Eldridge authored
      Remove overlapping inputForm=LowForm tests (bp #1753)
      d56cecd8
    • Schuyler Eldridge's avatar
      Simplify CustomTransformSpec · 3fd2a033
      Schuyler Eldridge authored
      
      
      Refactor the test used in the CustomTransformSpec to assert that
      inputForm=LowForm legacy transforms run right before the emitter (see
      note below!). The new test looks only for a list of (customTransform,
      emitter) in a sliding, size-2 window of the flattened transform order.
      Previously, this was looking for a match before and after the custom
      transform. The old implementation necessitate busywork updates of the
      test when new transforms are added that changed the transform running
      before the custom transform.
      
      Note: this test, as written is intentionally wrong. When the
      LegalizeAndReductionsTransform was added, this was placed after
      inputForm=LowForm and before the Verilog emitters. However, the test
      is supposed to ensure that an inputForm=LowForm transform runs
      immediately before its emitter. I'm intentionally leaving the test
      broken. This behavior can be changed in a follow-on commit if need be.
      
      Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>
      (cherry picked from commit debee429)
      3fd2a033
    • Schuyler Eldridge's avatar
      Remove overlapping inputForm=LowForm tests · eb467132
      Schuyler Eldridge authored
      
      
      Remove tests from LoweringCompilerSpec testing the placement of
      inputForm=LowForm legacy, custom transforms. This behavior is already
      tested in the CustomTransformSpec.
      
      Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>
      (cherry picked from commit f5dd8ddc)
      
      # Conflicts:
      #	src/test/scala/firrtlTests/LoweringCompilersSpec.scala
      eb467132
  8. Jul 15, 2020
    • mergify[bot]'s avatar
      Make TopWiringTransform run before LowerTypes (#1750) (#1768) · 954462f4
      mergify[bot] authored
      
      
      Add an optionalPrerequisiteOf to TopWiringTransform pointing at
      LowerTypes.
      
      This fixes a bug where top-wired wire bundles with flips could result
      in the top-wired, flattened bundle having every field with an "output"
      direction if the TopWiringTransform is moved around in the transform
      order (see FIRRTL issue #1744).
      
      Why did this happen?
      
      Fundamentally, this stems from the fact that LowerTypes preserves
      bundle direction for ports, but destroys it for wires.
      
      Specifically, The TopWiringTransform creates ports of the "output"
      direction that are copies of the underlying type of the component
      being top-wired. Before LowerTypes, the type of a bundle has direction
      information via flips. After LowerTypes, the lowered ground type does
      not have this information. Therefore, all the ports are ground type
      outputs. Simply ensuring that TopWiringTransform must run before
      LowerTypes avoids this problem.
      
      Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>
      
      Co-authored-by: default avatarmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
      (cherry picked from commit 005a3d16
      
      )
      
      Co-authored-by: default avatarSchuyler Eldridge <schuyler.eldridge@ibm.com>
      954462f4
  9. Jul 14, 2020
  10. Jun 26, 2020
  11. Jun 25, 2020
    • mergify[bot]'s avatar
      Build ArrayBuffers in Block.mapStmt (bp #1669) (#1684) · c07da8a5
      mergify[bot] authored
      
      
      * Build ArrayBuffers in Block.mapStmt (#1669)
      
      * Build ArrayBuffers in Block.mapStmt
      
      * Have empty Block serialize as "skip"
      
      The FIRRTL parser requires at least one indented line in each module.
      Sometimes tests emit and parse modules with no contents; this ensures
      there's always at least a "skip" in empty modules.
      
      Also fix tests that expected certain skips
      
      * Use var List as stack in Block.mapStmt impl
      
      This replaces Iterator concatenation. In Scala 2.11, RHS recursion on
      Iterators is not stack safe. This seems to have been fixed in 2.12 by
      Scala PR 5033.
      
      Co-authored-by: default avatarmergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
      (cherry picked from commit 1e497ce3
      
      )
      
      # Conflicts:
      #	src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala
      #	src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala
      
      * Fixup for 1.3.x
      
      Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      c07da8a5
  12. Jun 24, 2020
  13. Jun 23, 2020
  14. Jun 13, 2020
  15. Jun 10, 2020
  16. Jun 07, 2020
  17. Jun 04, 2020
  18. Jun 03, 2020
  19. May 31, 2020
    • mergify[bot]'s avatar
      Improve anno logging (bp #1639) (#1642) · 496d7bba
      mergify[bot] authored
      * DRY out transform running and annotation remapping
      
      (cherry picked from commit 1930b7b0)
      
      * Do not throw NonFatal exceptions in annotation logging
      
      If an annotation cannot be serialized by json4s, we should not throw
      exceptions when doing trace-level logging.
      
      (cherry picked from commit db7928a4
      
      )
      
      * Waive UpdateAnnotations.propagateAnnotations in Mima checks
      
      This method was package private, public from the Java perspective but
      private for Scala
      
      Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      496d7bba
  20. May 20, 2020
  21. May 19, 2020
  22. May 15, 2020
  23. May 14, 2020