- Aug 05, 2020
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Jack Koenig authored
Co-authored-by:Andrew Waterman <andrew@sifive.com>
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Jack Koenig authored
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- Aug 01, 2020
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mergify[bot] authored
* add sign-extend const-prop test * Emitter: don't wrap Neg operand in concat (cherry picked from commit b24b9a01 ) Co-authored-by:
Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
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Albert Chen authored
* add const prop bitwise reduction equivalence test * mask negative literals when propagating reduction * change widths * get rid of unnecessary if * add BigInt mask utility
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- Jul 31, 2020
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mergify[bot] authored
* test const prop of addition of negative literals * Emitter: handle minimum negative values correctly * update expected verilog in AsyncResetSpec (cherry picked from commit ea558ad7 ) Co-authored-by:
Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
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mergify[bot] authored
* ConstProp: test bitwise op of signed literals * ConstProp: use bit mask for FoldOr/FoldXor * handle and also * add UIntLiteral.masked helper Co-authored-by:
Jack Koenig <koenig@sifive.com> (cherry picked from commit 1927dc65 ) Co-authored-by:
Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
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- Jul 30, 2020
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mergify[bot] authored
* WiringUtils.sinksToSources: make sinkInsts order deterministic * WiringUtils: make owners a LinkedHashMap * Wiring: only make something a Wire if it isn't a port already Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit c02c9b7f ) Co-authored-by:
Kevin Laeufer <kevin.laeufer@sifive.com>
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- Jul 21, 2020
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Albert Chen authored
* add test to check that RemoveIntervals fixes kinds * RemoveIntervals: run ResolveKinds Co-authored-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Jul 18, 2020
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mergify[bot] authored
Add cross-building of unidoc to test issues if a user later does a +publishLocal (like with Chisel CI). Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit 5f70175d ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Jul 17, 2020
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Schuyler Eldridge authored
Remove overlapping inputForm=LowForm tests (bp #1753)
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Schuyler Eldridge authored
Refactor the test used in the CustomTransformSpec to assert that inputForm=LowForm legacy transforms run right before the emitter (see note below!). The new test looks only for a list of (customTransform, emitter) in a sliding, size-2 window of the flattened transform order. Previously, this was looking for a match before and after the custom transform. The old implementation necessitate busywork updates of the test when new transforms are added that changed the transform running before the custom transform. Note: this test, as written is intentionally wrong. When the LegalizeAndReductionsTransform was added, this was placed after inputForm=LowForm and before the Verilog emitters. However, the test is supposed to ensure that an inputForm=LowForm transform runs immediately before its emitter. I'm intentionally leaving the test broken. This behavior can be changed in a follow-on commit if need be. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit debee429)
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Schuyler Eldridge authored
Remove tests from LoweringCompilerSpec testing the placement of inputForm=LowForm legacy, custom transforms. This behavior is already tested in the CustomTransformSpec. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit f5dd8ddc) # Conflicts: # src/test/scala/firrtlTests/LoweringCompilersSpec.scala
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- Jul 15, 2020
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mergify[bot] authored
Add an optionalPrerequisiteOf to TopWiringTransform pointing at LowerTypes. This fixes a bug where top-wired wire bundles with flips could result in the top-wired, flattened bundle having every field with an "output" direction if the TopWiringTransform is moved around in the transform order (see FIRRTL issue #1744). Why did this happen? Fundamentally, this stems from the fact that LowerTypes preserves bundle direction for ports, but destroys it for wires. Specifically, The TopWiringTransform creates ports of the "output" direction that are copies of the underlying type of the component being top-wired. Before LowerTypes, the type of a bundle has direction information via flips. After LowerTypes, the lowered ground type does not have this information. Therefore, all the ports are ground type outputs. Simply ensuring that TopWiringTransform must run before LowerTypes avoids this problem. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 005a3d16 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Jul 14, 2020
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mergify[bot] authored
Changed from target/<scala-version>/src_managed/main/firrtl/ to target/<scala-version>/src_managed/main/compiled_protobuf/firrtl/ The protobuf generation clears its target directory so it would clear the generated ANTLR-generated files. (cherry picked from commit c14330d6 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 26, 2020
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mergify[bot] authored
* Batch renames in LowerTypes Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Add benchmarking for LowerTypes Add infrastructure of benchmarking Transforms (in addition to existing infra for Passes). Also run System.gc between each timed benchmark to improve stability. Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 87c5d034 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Jun 25, 2020
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mergify[bot] authored
* Build ArrayBuffers in Block.mapStmt (#1669) * Build ArrayBuffers in Block.mapStmt * Have empty Block serialize as "skip" The FIRRTL parser requires at least one indented line in each module. Sometimes tests emit and parse modules with no contents; this ensures there's always at least a "skip" in empty modules. Also fix tests that expected certain skips * Use var List as stack in Block.mapStmt impl This replaces Iterator concatenation. In Scala 2.11, RHS recursion on Iterators is not stack safe. This seems to have been fixed in 2.12 by Scala PR 5033. Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1e497ce3 ) # Conflicts: # src/test/scala/firrtlTests/annotationTests/EliminateTargetPathsSpec.scala # src/test/scala/firrtlTests/annotationTests/MorphismSpec.scala * Fixup for 1.3.x Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 24, 2020
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mergify[bot] authored
* Refactor benchmark_code_compile.py to have job running utility This provides a common Python interfaces for monitoring resource usage of subprocesses Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit 038faf9f ) * Add find_heap_bound.py script for finding minimum heap size Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit f7ae514f ) # Conflicts: # .travis.yml * Fixup for 1.3.x Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
* Don't Dedup modules if it would change semantics (#1713) If a module has ports of type Bundle that are used in aggregate connections in parent modules, Dedup cannot change the names of the fields of the Bundle or it would change the semantics of the connection. Dedup now detects this case and refrains from agnostifying the ports of such modules to prevent this issue. (cherry picked from commit e0e68568 ) # Conflicts: # src/main/scala/firrtl/transforms/Dedup.scala # src/test/scala/firrtlTests/transforms/DedupTests.scala * Fixup for 1.3.x Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
* Add support for ValidIf to ProtoBuf [de]serialization (cherry picked from commit d1db9067 ) * Fixup ProtoBuf ValidIf test for 1.3.x Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 23, 2020
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mergify[bot] authored
Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit a845a114 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Jun 13, 2020
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mergify[bot] authored
* delete usages of toSet for determinism * add formatting suggestion from code review (cherry picked from commit b750754c ) Co-authored-by:
Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
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- Jun 10, 2020
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mergify[bot] authored
* Use Travis Workspaces Add stage to build FIRRTL and share it with later steps running the tests * [CI] Do not sbt clean in formal_equiv.sh This change takes advantage of shared workspace in Travis Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1769f8d7 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
Use WrappedExpression instead of MemoizedHash. The benefit of memoizing the hash pales in comparison to the cost of hashing deeply nested Types in the AST. Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit bffc340e ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 07, 2020
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Jack Koenig authored
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- Jun 04, 2020
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mergify[bot] authored
* Generalize pattern of ResolveKindsBenchmark * Extend PassBenchmark to benchmark a particular Pass * Add license note to file (cherry picked from commit 88112433) * Use recursive-then-iterative approach for check_width_e * Avoid excessively deep recursion * Avoid overhead of DFS for shallow expression trees * Reduce work: skip expressions that cannot contain error-containing subtrees * Review feedback: added commentary to explain new check_widths_e structure (cherry picked from commit d7bd6d64 ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com>
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mergify[bot] authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Jun 03, 2020
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mergify[bot] authored
Revert: Generalize keyword collision to name manipulation, Add {Lower,Upper}CaseNames Transforms (#1651) (#1661) * Revert "Add test of {Lower, Upper}CaseNames" This reverts commit 93c078b8 . Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Add --change-name-case <lower|upper> option" This reverts commit d3ab7e2d . Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Add features.{LowerCaseNames, UpperCaseNames} transforms" This reverts commit c8dcdacf . Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> * Revert "Refactor RemoveKeywordCollisions->ManipulateNames" This reverts commit c534c5ab . Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit b4192bba ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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mergify[bot] authored
Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 97a8d824 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- May 31, 2020
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mergify[bot] authored
* DRY out transform running and annotation remapping (cherry picked from commit 1930b7b0) * Do not throw NonFatal exceptions in annotation logging If an annotation cannot be serialized by json4s, we should not throw exceptions when doing trace-level logging. (cherry picked from commit db7928a4 ) * Waive UpdateAnnotations.propagateAnnotations in Mima checks This method was package private, public from the Java perspective but private for Scala Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- May 20, 2020
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mergify[bot] authored
(cherry picked from commit 41d0d696 ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
(cherry picked from commit 20fac5ce ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com>
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- May 19, 2020
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mergify[bot] authored
* Fixes #1561 * Add test for zero-reset reg from #1561 (cherry picked from commit 8653734c ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Closes #1597 (cherry picked from commit 1cf446ce ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com>
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- May 15, 2020
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mergify[bot] authored
(cherry picked from commit ba03e2f6 ) Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
Generalize keyword collision to name manipulation, Add {Lower,Upper}CaseNames Transforms (bp #1592) (#1612) * Refactor RemoveKeywordCollisions->ManipulateNames Generalize the operations of the RemoveKeywordCollisions transform into a new ManipulateNames transform. The ManipulateNames transform is an abstract transform for making conditional modifications to keywords/names in a FIRRTL circuit. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit c534c5ab ) * Add features.{LowerCaseNames, UpperCaseNames} transforms Creates the features package and populates it with two new transforms: LowerCaseNames and UpperCaseNames. These transforms convert all names in a FIRRTL circuit to lower case or upper case. This is intended to help align generated Verilog with the policies of the company/institution using it. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> squash! Add LowerCaseNames and UpperCaseNames transforms (cherry picked from commit c8dcdacf ) * Add --change-name-case <lower|upper> option Adds an options to the FIRRTL compiler command line to schedule the LowerCaseNames and UpperCaseNames transforms. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit d3ab7e2d ) * Add test of {Lower, Upper}CaseNames Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> (cherry picked from commit 93c078b8 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Add benchmark for ResolveKinds with hot JIT * Use HashMap instead of LinkedHashMap in ResolveKinds * Modify to deprecate old methods for backport (cherry picked from commit 0f78e2df ) Co-authored-by:
Albert Magyar <albert.magyar@gmail.com> * Eliminate unnecessary traversals in ResolveKinds * Modify for backporting * Make find_port return Unit and use Foreachers in ResolveKinds * Modify for backporting Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
Albert Magyar <albert.magyar@gmail.com>
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- May 14, 2020
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mergify[bot] authored
* Remove expensive .distinct in Dedup (cherry picked from commit 36227e96) * Remove accidental hashing of all Modules in Dedup (cherry picked from commit 71e922c0 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
* Use HashMap instead of LinkedHashMap in InferTypes Do the same in CInferTypes (cherry picked from commit a15f65c8) * Remove a redundant Expression traversal in InferTypes (cherry picked from commit 26693f72 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
Co-authored-by:
Scala Steward <me@scala-steward.org> Co-authored-by:
Scala Steward <43047562+scala-steward@users.noreply.github.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit d6e3cd00 ) Co-authored-by:
Jim Lawson <ucbjrl@berkeley.edu>
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mergify[bot] authored
* Update scalacheck-1-14 to 3.1.1.1 (#1606) Co-authored-by:
Scala Steward <me@scala-steward.org> Co-authored-by:
Scala Steward <43047562+scala-steward@users.noreply.github.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 50a90664 ) # Conflicts: # build.sbt # build.sc * Fix broken merge Co-authored-by:
Jim Lawson <ucbjrl@berkeley.edu>
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