Add features.{LowerCaseNames, UpperCaseNames} transforms

Creates the features package and populates it with two new transforms:
LowerCaseNames and UpperCaseNames. These transforms convert all names
in a FIRRTL circuit to lower case or upper case. This is intended to
help align generated Verilog with the policies of the
company/institution using it.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

squash! Add LowerCaseNames and UpperCaseNames transforms