- Nov 10, 2019
-
-
Jack Koenig authored
-
Jack Koenig authored
-
- Nov 07, 2019
-
-
Jack Koenig authored
-
Schuyler Eldridge authored
Add separate Issue and PR templates
-
Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
- Nov 06, 2019
-
-
Jack Koenig authored
Recursive literal lookup needs to be guarded against combinational loops Added a test-case to illustrate the issue when CheckResets is run before CheckCombLoops
-
Jack Koenig authored
-
- Nov 05, 2019
-
-
David Biancolin authored
Supply a trait to allow user annotations to provide JsonProtocol type hints
-
Jack Koenig authored
-
Albert Magyar authored
* Closes #1162 * Instances of extmodules remain in the final hierarchy * Extmodule definitions are not renamed or duplicated * The rest of the pass may proceed as normal
-
Albert Magyar authored
* Fixes #1154 * Tests that #1154 example produces SyntaxErrorsException * Generally helps catch trailing syntax errors * Performance-neutral relative to previous grammar * Recommended by antlr4 devs, can help performance in some cases * See antlr/antlr4#1540
-
- Nov 01, 2019
-
-
Jack Koenig authored
Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS
-
Jack Koenig authored
-
Albert Magyar authored
Change findInstancesInHierarchy to return implicit top instance
-
- Oct 31, 2019
-
-
David Biancolin authored
-
- Oct 30, 2019
-
-
David Biancolin authored
-
David Biancolin authored
-
David Biancolin authored
Co-Authored-By:Jack Koenig <koenig@sifive.com>
-
David Biancolin authored
-
David Biancolin authored
-
Albert Magyar authored
* Change FIRRTL-internal API, affecting only one corner case * Make API more "DWIM" and consistent with other methods * Add test cases for findInstancesInHierarchy * Update Scaladoc
-
- Oct 26, 2019
-
-
David Biancolin authored
-
- Oct 25, 2019
-
-
Albert Magyar authored
Enhance CheckCombLoops errors with connection info
-
Albert Magyar authored
* Closes #1203
-
Albert Magyar authored
* Add Scaladoc for EdgeData API * Include stringified vertices in EdgeNotFoundException
-
David Biancolin authored
-
- Oct 22, 2019
-
-
Schuyler Eldridge authored
Emit Verilog else-if for Register Updates
-
Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Schuyler Eldridge authored
Modifies the Verilog emitter to emit "else if" blocks as opposed to more deeply nested "else begin if" blocks. This improves the output Verilog readability. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Albert Magyar authored
Fix handling of read enables for write-first (default) memories in VerilogMemDelays
-
Albert Magyar authored
-
Albert Magyar authored
-
Albert Magyar authored
-
Albert Magyar authored
* Additional refactoring to clean up pass implementation * Make register names match old scheme to appease CI
-
- Oct 19, 2019
-
-
Adam Izraelevitz authored
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
-
- Oct 10, 2019
-
-
Schuyler Eldridge authored
Make TopWiringTransform Idempotent
-
- Oct 09, 2019
-
-
Schuyler Eldridge authored
Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
Schuyler Eldridge authored
This changes TopWiringTransform to remove TopWiringAnnotations after it runs. Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
-
- Oct 08, 2019
-
-
Albert Magyar authored
* Replace instance analysis code with InstanceGraph API calls * Add convenience implicits for using TargetTokens as safe boxed strings
-
- Oct 04, 2019
-
-
Albert Magyar authored
-