Skip to content
GitLab
Projects
Groups
Topics
Snippets
/
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
Menu
github.com
freechipsproject
firrtl
Commits
28ffacca
Commit
28ffacca
authored
Oct 30, 2019
by
Jack Koenig
Browse files
Guard initial blocks in emitted Verilog with `ifndef SYNTHESIS
parent
68964fed
Changes
2
Hide whitespace changes
Inline
Side-by-side
Mirrors-Admin
@mirrors-admin
mentioned in commit
ff73a760
·
Jun 19, 2023
mentioned in commit
ff73a760
mentioned in commit ff73a760c5a03209ef8473d87d938808ad552e1b
Toggle commit list
Preview
Supports
Markdown
0%
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment