Disallow memory ports being declared in a when scope and referenced
elsewhere.  Add one test of this behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Update the ICache.fir regression test from Rocket Chip.  This was built
using Chisel3 3.4.3 with an unmerged fix that includes a wire to avoid
letting an mport escape the when scope in which it is defined.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Add --start-from option (#2273)

Add a new option to the FIRRTL compiler, "--start-from = <form>".  If
used, this will cause the compiler to assume that the input FIRRTL
circuit is already in the specific form.  It will then skip unnecessary
passes given this information.

E.g., if a user requests to run "firrtl -X verilog --start-from low"
then the compiler will only run transforms necessary to get from low
FIRRTL to Verilog.  Transforms necessary for ingesting FIRRTL IR will be
run if needed (checks and type/kind/flow resolution).

To implement this, a CurrentFirrtlStateAnnotation is added.  Advanced
users can use this directly to tell the FIRRTL compiler exactly what
transforms have already been run, including the ability to ignore checks
or type/kind/flow resolution if they so desire.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit c7eaa67d

)

* Waive bincompat issues that don't affect Scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Fix VerilogMemDelays use before declaration (#2278)

The pass injects pipe registers immediately after the declaration of the
memory. This can be problematic if the clock for the associated memory
port is defined after the declaration of the memory. For any memory port
clocks that are driven by non-ports, we now inject a wire before the
pipe register declarations to be sure there are no
use-before-declaration issues.

(cherry picked from commit 11128d93

)

# Conflicts:
#	src/main/scala/firrtl/passes/memlib/VerilogMemDelays.scala

* Fix merge conflicts

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add Protocol Buffer emission export

This adds infrastructure and annotations that let a user emit a FIRRTL
circuit as a Protocol Buffer.

Fixes #1696.

(cherry picked from commit d708d3f0

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add a compiler/emitter that can target minimal high form.  This will
produce output that only has CHIRRTL constructs removed.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 3ea95e72

)

# Conflicts:
#	src/test/scala/firrtlTests/stage/FirrtlMainSpec.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Replace mem macros renaming (#2243)

* ReplaceMemMacros: add target rename test case

* ReplaceMemMacros: rename references to instances

* fix renaming for deduped mems

* use grouped DummyAnnos to preserve order

* Apply suggestions from code review

Co-authored-by: Jack Koenig <koenig@sifive.com>

* run scalafmt

* flatten targets

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit 62fdb87e

)

# Conflicts:
#	src/main/scala/firrtl/passes/memlib/ReplaceMemMacros.scala

* fix conflicts

* add back old APIs, add new private methods

Co-authored-by: Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
Co-authored-by: Albert Chen <albert.chen@sifive.com>

(cherry picked from commit 117b84a1

)

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Fix renaming of local targets in InlineInstances (#2238)

* add more inline renaming test cases

* InlineInstances: fix renaming for local targets

* run scalafmt

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 15309c97

)

# Conflicts:
#	src/main/scala/firrtl/passes/Inline.scala

* Resolve backport conflicts

Co-authored-by: Albert Chen <40366337+albertchen-sifive@users.noreply.github.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit d35248c8

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>

* Improve performance of RenameMap in LowerTypes (#2233)

LowerTypes creates a lot of mappings for the RenameMap. The built-in
.distinct of renames becomes a performance program for designs with
deeply nested Aggregates. Because LowerTypes does not create duplicate
renames, it can safely eschew the safety of using .distinct via a
private internal API.

(cherry picked from commit e0844966

)

* Waive bincompat issue that isn't visible from Scala

Co-authored-by: Jack Koenig <koenig@sifive.com>

This function will safely wrap any unserializeable annotations in
UnserializeableAnnotations so that they can be safely serialized to JSON
for logging.

(cherry picked from commit c2d72fd8

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 6db311b3

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 33c0b431

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

Looks like a typo/auto-merge hiccup.

(cherry picked from commit adc2ad9a

)

Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>

(cherry picked from commit bf1cf3d2

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Constant propagation of the Xor op folds `xor(a, SInt(0))` to
`asUInt(a)`. For comparison, Or folds to `asUInt(pad(a, W))`. This can
be a problem in the following case:

    circuit Foo :
      module Foo :
        input a: UInt<3>
        output b: UInt<4>
        b <= asUInt(xor(asSInt(a), SInt<4>(0)))

This would emit the assignment as `b = a` instead of the sign-extended
`b = {{1{a[2]}},a}`.

This requires adjusting the `pad(e, t)` function use in const prop,
which currently just inserts a `Pad` prim op with the requested output
type. However, the function advertises that it pads *to the width* of
the type `t`. Some of the folds rely on this and request the padding of
a SInt<N> to the width of a UInt<M>. But the current implementation then
then actually returns a `Pad` op with type UInt<M>, instead of the
SInt<M> that was requested.

(cherry picked from commit e9b2946c

)

Co-authored-by: Fabian Schuiki <fabian@schuiki.ch>

Add indent parameter to Serializer.serialize() (backport #2177)

Using Utils.indent() gives deprecation warnings to use Serializer instead. However,
the Serializer class itself doesn't provide a means to manually indent a FirrtlNode
string a certain number of times.

The indent variable, previously hardcoded to 0, is now exposed as a second parameter
for the modified serialize function, and the old serialize function just calls the
modified serialize with indents = 0 for binary compatibility

Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 20890bbd)

This PR adds options for memory initialization inside or outside the
`ifndef SYNTHESIS` block.

(cherry picked from commit d0d3cd4e

)

Co-authored-by: Carlos Eduardo <me@carlosedp.com>
Co-authored-by: Jack Koenig <koenig@sifive.com>

To maintain binary compatibility, InlineAcrossCasts is just aliases to
the now deprecated InlineCasts. We can make the binary incompatible
change of renaming the class and object for 1.5.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 9a3dcf76

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

CSESubAccesses was intended to be a simple workaround for a quadratic
performance bug in RemoveAccesses but ended up having tricky corner
cases and was hard to get right. The solution to the RemoveAccesses
bug--quadratic expansion of dynamic indexes of vecs of aggreate
type--turned out to be quite simple and makes CSESubAccesses much less
useful and not worth fixing.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit a41af6f0

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* add --no-constant-propagation to disable constant propagation

* add test

* deprecate DisableFold.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit abeff01f

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* Fix bug in zero-width memory removal

Correctly remove all extraneous connections to all types of memory
ports (read, write, readwrite) for zero-width memories.  Previously,
only read ports were correctly handled.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* fixup! Fix bug in zero-width memory removal

(cherry picked from commit 67ce97a1

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This fixes an error with negating a negative SInt literal and a
[debatable] lint warning in Verilator when negating any value.

This behavior matches that of Chisel (which directly emits the 0 - x
already).

(cherry picked from commit 49b82324

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Previously, InlineCasts could inline complex (ie. non-cast) Expressions
into other complex Expressions. Now it will only inline so long as there
no more than 1 complex Expression in the current nested Expression.

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
(cherry picked from commit b274b319

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Due to inlining of Boolean expressions, the following circuit is handled
directly by the VerilogEmitter:

input a: UInt<4>
input b: SInt<1>
output o: UInt<5>
o <= dshl(a, asUInt(cvt(b)))

Priot to this change, this could crash due to mishandling of cvt in the
logic to inject parentheses based on Verilog precedence rules.

This is a corner case, but similar bugs would drop up if we open up the
VerilogEmitter to more expression inlining.

(cherry picked from commit 94d1bee4

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 0eb7afd0

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Previously, concatenating two SInts where one is of zero-width would
return the non-zero-width SInt. This is incorrect because the output of
Cat should be of type UInt. Now the ZeroWidth transform will introduce a
cast when removing a Cat when the argument type is non-UInt.

(cherry picked from commit fd55c51b

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

The flow of a LHS SubAccess node may still be SourceFlow if the type of
the Vec element has a flip. Tweak the logic of CSESubAccesses to check
every Expression flow while recursing instead of just the flow of the
final SubAccess.

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit ed1eb88d

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit aa24fe3e

)

Co-authored-by: Carlos Eduardo <me@carlosedp.com>

This PR adds a new annotation allowing inline loading for memory files
in Verilog code.

(cherry picked from commit efdefde2

)

Co-authored-by: Carlos Eduardo <carlosedp@gmail.com>

* Fix ProtoBuf conversions for Verification IR (#2100)

(cherry picked from commit 5be1abb4

)

* waiving issues (#2103)

Co-authored-by: Deborah Soung <debs@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Fixes n^2 performance problem when dynamically indexing Vecs of
aggregate types.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit e58ba0c1

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Bumping Scala minor version but not bumping CI guards on the version
causes tests to no longer run. Change to using startsWith(...) so that
minor version bumps won't cause issues in the future.

Also run ScalaFmt

(cherry picked from commit 541a70c9)

* Add DiGraph factory method and prettyTree

* New factory method enables direct construction of DiGraphs from edges
* DiGraph.prettyTree enables visualization of tree or multi-tree
  diagraphs

(cherry picked from commit 5ea82302)

* Add MustDeduplicateTransform

This enables marking modules as "must deduplicate". If modules marked as
such do not deduplicate, the transform will create error reports and
make suggestions as to why deduplication failed.

(cherry picked from commit 5903e6a3

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* fix a test not detecting verilog name conflicts.

(cherry picked from commit 48e56c9f)

* bug fix for VerilogPrep using wrong type.

(cherry picked from commit b2726dff)

* fix for LoweringCompilersSpec.

(cherry picked from commit 61f3e886

)

Co-authored-by: Jiuyang liu <liujiuyang1994@gmail.com>

Signed-off-by: Jean Bruant <jean.bruant@ovhcloud.com>
(cherry picked from commit 6e0e7605

)

Co-authored-by: John's Brew <46595442+johnsbrew@users.noreply.github.com>