- Oct 29, 2021
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mergify[bot] authored
Previously, the example had an extra wrapping module that led to the interesting example getting optimized away. (cherry picked from commit 84da5fdb ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Oct 23, 2021
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mergify[bot] authored
* Update bundles-and-vecs.md * Update docs/src/explanations/bundles-and-vecs.md Co-authored-by:
Megan Wachs <megan@sifive.com> * Update naming.md Added a title to the cookbook * Add name to Multiple Clock Domain page * Update multi-clock.md Co-authored-by:
Megan Wachs <megan@sifive.com> (cherry picked from commit 9c026fd3 ) Co-authored-by:
Shorla <77856859+Shorla@users.noreply.github.com>
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- Oct 21, 2021
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mergify[bot] authored
* Update computeName and callsites (#2192) Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit d6907893 ) # Conflicts: # core/src/main/scala/chisel3/internal/Builder.scala * Mergify/bp/3.4.x/pr-2192 Deprecate computeName (#2198) * Fix merge conflict * Restore public API for computeName and deprecate it * Build waiver Co-authored-by:
Aditya Naik <91489422+adkian-sifive@users.noreply.github.com> Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Oct 15, 2021
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mergify[bot] authored
* Update docs README with instructions for new pages * Update docs/README.md (cherry picked from commit 7931172c ) Co-authored-by:
Megan Wachs <megan@sifive.com>
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- Oct 13, 2021
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mergify[bot] authored
* Update bundles-and-vecs.md * Update docs/src/explanations/bundles-and-vecs.md Co-authored-by:
Megan Wachs <megan@sifive.com> Co-authored-by:
Megan Wachs <megan@sifive.com> (cherry picked from commit ce8e4207 ) Co-authored-by:
Shorla <77856859+Shorla@users.noreply.github.com>
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mergify[bot] authored
* Update experimental-features.md Added title to Experimental features * Update experimental-features.md * Update docs/src/appendix/experimental-features.md Co-authored-by:
Megan Wachs <megan@sifive.com> Co-authored-by:
Megan Wachs <megan@sifive.com> (cherry picked from commit 463a352e ) Co-authored-by:
Abongwa Bonalais <81782853+Burnleydev1@users.noreply.github.com>
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- Oct 12, 2021
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mergify[bot] authored
* Added title * Update docs/src/explanations/blackboxes.md Co-authored-by:
Megan Wachs <megan@sifive.com> Co-authored-by:
Megan Wachs <megan@sifive.com> (cherry picked from commit d06ba691 ) Co-authored-by:
Abongwa Bonalais <81782853+Burnleydev1@users.noreply.github.com>
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- Oct 11, 2021
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mergify[bot] authored
* Update developer documentation in README (#2160) (cherry picked from commit 3643b7ba ) # Conflicts: # README.md * Update README.md Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
Megan Wachs <megan@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
Added title to "Namimg Cookbook" website. Co-authored-by:
Megan Wachs <megan@sifive.com> (cherry picked from commit 2439974e ) Co-authored-by:
Abongwa Bonalais <81782853+Burnleydev1@users.noreply.github.com>
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- Oct 07, 2021
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mergify[bot] authored
* Remove all Bundle cloneTypes and chiselRuntimeDeprecate its use (#2052) * Remove all manual cloneTypes and make it chisel runtime deprecated to add one * runtime deprecate cloneType with runtime reflection * [Backport this commit] Bundle: add check that override def cloneType still works (will be made an error later) * Plugin: make it an error to override cloneType and add a test for that * Docs: can't compile the cloneType anymore * BundleSpec: comment out failing test I cannot get to fail or ignore Co-authored-by:
Jack Koenig <koenig@sifive.com> (cherry picked from commit ce15ad50 ) # Conflicts: # src/test/scala/chiselTests/BundleSpec.scala * BundleSpec: fix merge conflict and change test to check that it does compile with a cloneType, just a warning not an error * Downgrade warning to error * restore import that is still needed on the backport * Put back override def cloneType * Checkpoint -- tests pass but with more errors than one would expect * Bundle Spec: tests still passing despite throwing runtime deprecation errors * BundleSpec: clean up some assertTesterPasses so I can check they don't have the runtime exception * bundles-and-vecs: docs now more strict about warnings * BundleSpec: stop trying to test plugin things because 2.11 doesn't use plugin Co-authored-by:
Megan Wachs <megan@sifive.com>
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- Oct 06, 2021
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mergify[bot] authored
* Turn on fatal warnings in mdoc documentation (#2146) (cherry picked from commit df76831c ) # Conflicts: # build.sbt * Resolve merge conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Oct 05, 2021
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mergify[bot] authored
Close #2138 (cherry picked from commit 7360c815 ) Co-authored-by:
Nick <handnf@gmail.com>
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- Sep 18, 2021
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Jack Koenig authored
Also update binary compatibility checking to 3.4.4
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- Sep 16, 2021
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mergify[bot] authored
(cherry picked from commit 1ae18008 ) Co-authored-by:
Adam Izraelevitz <adam.izraelevitz@sifive.com>
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- Sep 09, 2021
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mergify[bot] authored
* Fix a bug causes incorrect pla generation when input is `?` (backport #2113) (#2118)Add a test case to demonstrate the bug found in #2112 (cherry picked from commit 89679a3c) * Test case rework (cherry picked from commit 0ca4ce23) * Fix #2112, handle `?->1` case (cherry picked from commit 189da982 ) * Remove trailing comma Co-authored-by:
mergify-bot <noreply@mergify.io> Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
* Update sbt installation instructions The bintray reference is dead. * fix grammar (cherry picked from commit ff1bcb09 ) Co-authored-by:
Martin Schoeberl <martin@jopdesign.com>
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- Aug 31, 2021
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mergify[bot] authored
Previous incomplete fixes in #2023 and #2031. The legality of a FIRRTL connection is determined by type and flow. Chisel does not have access to true flow information. Previous fix attempts tried to use ActualDirection as a stand-in for flow, but it is incorrect in many cases. This new approach checks the flows of the lvalue and rvalues in the connect and flips the connection if either the lvalue cannot be a sink or the rvalue cannot be a source. (cherry picked from commit 7fb2c1eb ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
(cherry picked from commit 29665743 ) Co-authored-by:
Kevin Laeufer <laeufer@cs.berkeley.edu>
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- Aug 30, 2021
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mergify[bot] authored
(cherry picked from commit 0a985f7d ) Co-authored-by:
Megan Wachs <megan@sifive.com>
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- Aug 25, 2021
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mergify[bot] authored
* Remove chisel3's own firrtl Emitter, use firrtl Serializer This will be slightly slower as it involves converting from Chisel modules to FIRRTL modules before turning them into Strings. This cost is somewhat mitigated by doing that conversion lazily such that we never materialize the entire firrtl Circuit in memory, only 1 module at a time. (cherry picked from commit 73bd4ee6) # Conflicts: # src/main/scala/chisel3/internal/firrtl/Emitter.scala # src/test/scala/chiselTests/PrintableSpec.scala # src/test/scala/chiselTests/VecLiteralSpec.scala # src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala * Emit .fir lazily, overcomes JVM 2 GiB String limit (cherry picked from commit d9c30ea0) # Conflicts: # src/main/scala/chisel3/internal/firrtl/Emitter.scala * Use BufferedCustomFileEmission in CircuitSerializationAnnotation (cherry picked from commit a6eb2ad8 ) * Resolve backport conflicts * Waive binary compatibility issues Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Aug 18, 2021
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mergify[bot] authored
* [docs] Add example of stripping directions from type * Apply suggestions from code review Co-authored-by:
Megan Wachs <megan@sifive.com> * Improve := comment Co-authored-by:
Megan Wachs <megan@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit e14bcb14 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Aug 06, 2021
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mergify[bot] authored
* Small changes to memory doc - Fixed typo "except" => "accept" - Use `Counter` explicitly in ROM section example. * Fix counter doc compile error * remove invisible doc block in memory example * more small fixes to make mem example pass doc compile * Get rid of sine wave iterator in memory doc * get rid of tabs on VecInit example * get rid of tabs on VecInit example (cherry picked from commit 75c00606 ) Co-authored-by:
Chick Markley <chick@qrhino.com>
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- Jul 23, 2021
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mergify[bot] authored
The example in the README is a sum, not an average. (cherry picked from commit 3f007bec ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jul 15, 2021
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mergify[bot] authored
Co-authored-by:
Jack Koenig <koenig@sifive.com> (cherry picked from commit e6c902ea ) Co-authored-by:
Leway Colin <colin4124@gmail.com>
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- Jul 10, 2021
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mergify[bot] authored
* Add `isOneOf` method to `ChiselEnum` (#1966) * Add @ekiwi's code as a starting point * Add test for ChiselEnum isOneOf method * Make isOneOfTester naming consistent with other testers * Add scaladoc comments for isOneOf * Add isOneOf tests that use the method that takes variable number of args * Add guide level documentation example for isOneOf (cherry picked from commit bb520b85 ) * Turn on autoclonetype2 for mdocs Co-authored-by:
Verneri Hirvonen <11316555+chiplet@users.noreply.github.com> Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031) PR #2023 fixed a composition issue for chisel3 biconnects delegating to FIRRTL partial connect when compatibility mode Bundles are elements of chisel3 Bundles. It missed an important case though that caused previously working code to break. The bug is fixed by doing the automatic flipping for compatibility mode Bundles that have "Input" as a direction in addition to those that are "Flipped". (cherry picked from commit 5183ef88 ) # Conflicts: # src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala * Resolve backport conflicts Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jul 09, 2021
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mergify[bot] authored
* Make it legal for concrete resets to drive abstract reset (#2018) This has been legal in FIRRTL since v1.2.3 (when reset inference started using a unification-style algorithm) but was never exposed in the Chisel API. Also delete the overridden connects in AsyncReset and ResetType which just duplicate logic from MonoConnect. (cherry picked from commit 4b7b771e ) * Fix issues with tests Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
* Fix chisel3 <> for Bundles that contain compatibility Bundles (#2023) BiConnect in chisel3 delegates to FIRRTL <- semantics whenever it hits a Bundle defined in `import Chisel._`. Because chisel3 <> is commutative it needs to be mindful of flippedness when emitting a FIRRTL <- (which is *not* commutative). (cherry picked from commit 16c0b53e ) * Fix test issue in Scala 2.11 Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jul 08, 2021
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mergify[bot] authored
Change the Scaladoc for the dontTouch utility. Indicate that this is an _optimization barrier_ and not just a guarantee that the signal won't be removed. The optimization barrier interpretation is the current implementation in the Scala FIRRTL Compiler. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit f1e37900 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com>
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mergify[bot] authored
Also add newline to end of `verilog` modifier code blocks so that there is always a newline between code blocks and following material. (cherry picked from commit 558df41d ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jul 07, 2021
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mergify[bot] authored
* Change Chisel warnings to use logger instead of println It also uses the same logger as the Builder so that if we ever refactor that to be passed as an argument, it will be the same logger for both Builder and warning reporting. (cherry picked from commit 04caf395) * Add ChiselEnum.safe factory method and avoid warning Previously, ChiselEnum would warn any time a UInt is converted to an Enum. There was no way to suppress this warning. Now there is a factory method (`.safe`) that does not warn and returns (Enum, Bool) where the Bool is the result of calling .isValid on an Enum object. The regular UInt cast is also now smarter and will not warn if all bitvectors of the width of the Enum are legal states. (cherry picked from commit 5fe539c7) # Conflicts: # src/test/scala/chiselTests/ChiselSpec.scala * Update docs for ChiselEnum (cherry picked from commit bfb77d4c ) * Resolve merge conflicts and waive false bincompat issue Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 30, 2021
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mergify[bot] authored
* Restore aop.Select behavior for CloneModuleAsRecord (cherry picked from commit 0531cb53) * Change behavior of aop.Select to not include CloneModuleAsRecord Previously, CloneModuleAsRecord clones would result in the same BaseModule object coming up multiple times when using APIs like .instances, .collectDeep, and .getDeep. This was not the intended behavior and can lead to very subtle bugs. (cherry picked from commit 25a84b56 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 29, 2021
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mergify[bot] authored
* Fix CloneModuleAsRecord support for .toTarget (cherry picked from commit d3e13ce2) # Conflicts: # core/src/main/scala/chisel3/RawModule.scala * Set refs for ModuleClone and ClonePorts in less hacky way (cherry picked from commit b87107ad ) * Fixup for backport * Resolve merge conflicts * Fix semantic meaning change of Module -> MultiIOModule on master * Waive bincompat errors that cannot impact Scala users Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
(cherry picked from commit 44c7fca8 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
(cherry picked from commit 6a806918 ) Co-authored-by:
Jiuyang Liu <liu@jiuyang.me>
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mergify[bot] authored
(cherry picked from commit a5cfd8bf ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 26, 2021
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mergify[bot] authored
* Add Clock * Add Analog * Add Interval * Add line from User Types (...) to Record (cherry picked from commit 5e8ef455 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Jun 24, 2021
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mergify[bot] authored
Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 04de237e ) Co-authored-by:
Jiuyang Liu <liu@jiuyang.me>
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- Jun 15, 2021
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mergify[bot] authored
* explain sub-projects * Update README.md Co-authored-by:
Megan Wachs <megan@sifive.com> Co-authored-by:
Megan Wachs <megan@sifive.com> (cherry picked from commit ea84a176 ) Co-authored-by:
Deborah Soung <debs@sifive.com>
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mergify[bot] authored
(cherry picked from commit ac31c62e ) Co-authored-by:
Jiuyang Liu <liu@jiuyang.me>
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