Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove the "wiring" library and the WiringTransform SFC implementation.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove the "clocklist" package and all associated infrastructure.  This
removes the annotations associated with "clocklist" because they are
unsupported by the MFC.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove ReplSeqMem and related passes.  Prune memlib down to only
Annotations and utilities that are used by other areas of the SFC
codebase.

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Delete experimental backends only supported by the SFC and IR they
introduced.  This roughly covers three features:

  - RTLIL backend
  - BTOR2 backend
  - DefRandom non-standard FIRRTL IR node

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove the integrationTests project and directory.  These are formal
tests using unsupported SFC-only features of ChiselTest that are not
supported in Chisel 5.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove deprecated forceName Chisel APIs that operate on a component (as
opposed to a module/instance).  Remove the SFC transform associated
with this API.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove the SFC LoadMemoryTransform and update associated annotations to
not emit RunFirrtlTransformAnnotations.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove old "notes" directory from FIRRTL.  This includes a lot of great
brainstorming and feedback from early users of FIRRTL.  It doesn't need
to stay in the repo, however.  Fortunately, git will remember...

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

A number of deprecated features are removed from Chisel.  This includes
the following:

  - Interval types
  - FixedPoint types
  - Chisel compatibility module (import Chisel._)

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change the Scala build to use the FIRRTL subproject that was just
brought in-tree.  This removes the dependency of Chisel on the published
version of FIRRTL.  This work is done in preparation to remove the
Scala-based FIRRTL Compiler (SFC) from Chisel.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>

[chisel5] git subtree add FIRRTL

git-subtree-dir: firrtl
git-subtree-mainline: 9f416dda
git-subtree-split: 6a999e30

* Get rid of warnings in / doc build
  Many `[[...]]` dont work so replace with back-ticks
  Printable docs are very problematic, use Warning suppression for those
* Enable fatal warnings in CI for ScalaDoc generation

Co-authored-by: Jack Koenig <koenig@sifive.com>

This includes new command-line option --source-root which allows the
user of Chisel to point to one or more root directories for source files.
If no --source-root arguments are provided, it will default to using
"." which should work for typical SBT and Mill projects.

- Use regular expressions to get version strings more rigorously
- Add version discriminant function, you can compare version size
- Correct the version comparison of antlr under special conditions
- Improve the version comparison of protoc

Signed-off-by: Huang Rui <vowstar@gmail.com>

Flag is `-DdisableFatalWarnings`
Add flag to a number of places in build.sbt

Also check ScalaDoc generation in CI

* In BoringUtils replace deprecated SyncVar with BuilderContextCache
* Handle potential in-exhaustive match error
* Changes lines to linesIterator to fix deprecation warning
* Change build.sbt to make fatal warnings error come after suppressed warnings

Fix a bug where "--split-verilog" was not properly passed into the
CIRCTOptions struct.  Add a test to lock in the correct behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Deprecate ProtoBufFileFormat and warn if a user is doing Protobuf
emission.  This will be ripped out in Chisel 5.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove an unnecessary "currentState" argument when constructing the
internal PhaseManager of CIRCTStage.  This is no longer necessary given
that CIRCTState doesn't have to interoperate with SFC in any way.

This enables removal of this phase on the chisel5 branch.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Remove a bunch of unnecessary code that depends on SFC features from the
AnnotatingDiamondSpec.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Add an option to "circt.stage.ChiselStage", "--split-verilog", which
replaces the janky "firrt.EmitAllModulesAnnotation" method of generating
one-file-per-module output and output file splitting in "firtool".
Leave in the old behavior as a run-time warning until this gets removed
sometime after the Chisel 5 release.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Deprecate CIRCTStage and CIRCTMain.  These are stage-based wrappers
around just running firtool that are roughly equivalent to FirrtlStage
and FirrtlMain that did this for the SFC.  These do not have users and
it is unclear why these should persist given that
circt.stage.ChiselStage subsumes almost all use cases (going Chisel to
Verilog or Chisel to CHIRRTL and then using the build system to go from
CHIRRTL to Verilog).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove an unnecessary optionalPrerequisite of CIRCTStage on the SFC
Compiler phase.  This is entirely unnecessary given that there is no
longer an SFC -> MFC handoff path within CIRCT-based Chisel compilation
flows.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Deprecate this Annotation/Option which is only used by
chisel3.stage.ChiselStage.  An equivalent effect can be had with the
emitCHIRRTL method of the ChiselStage$ object or using the "--target
chirrtl" option of the ChiselStage class.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Modify tests, other than ChiselStageSpec, to all use
circt.stage.ChiselStage and not chisel3.stage.ChiselStage.  This paves
the way for the deletion of the latter in Chisel 5.

Note: there is one bug in the Trace API resulting in a commented out
test.  This is tracked with this CIRCT issue:

  - https://github.com/llvm/circt/issues/4661



Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>