Add "--split-verilog" circt.*.ChiselStage option (#3026)

Add an option to "circt.stage.ChiselStage", "--split-verilog", which
replaces the janky "firrt.EmitAllModulesAnnotation" method of generating
one-file-per-module output and output file splitting in "firtool".
Leave in the old behavior as a run-time warning until this gets removed
sometime after the Chisel 5 release.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>