Remove var from object Counter.apply, using a Wire instead. Also improve
some ScalaDoc and the class Counter require message.

(cherry picked from commit a39d0e13

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit e55c00fe)

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 6263fcc5

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Change the logic for determining which nested ChiselException cause to
use for a trimmed stack trace. Previously, this would use the
outermost. This commit changes this to use the innermost.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 5d269ce3

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Wrap elaboration in ChiselException

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

squash! Wrap elaboration in ChiselException

(cherry picked from commit d67c4100

)

* Report trimmed stack trace of Builder cause

Changes the behavior of ChiselException stack trace trimming to use
either the first exception that includes a method from the Builder or
the outer exception.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 73974725

)

* Test nested ChiselException in ChiselMain

Adds two tests:

  1. Test that an internal requirement failure (a bare exception) inside
     a Builder is properly reported/trimmed by ChsielStage/ChiselMain
  2. Test that the full stack trace includes the ChiselException

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 18520bf1

)

* Code style improvement

Co-authored-by: Jack Koenig <koenig@sifive.com>
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 30a0a5f9

)

* Safer generation of ChiselException.builderName

Change ChiselException.builderName to compute the name of Chisel's
internal Builder as opposed to hard-coding this with a string.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 969a56d6

)

* Add Scaladoc to ChiselException

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 3171cdf8

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit aac6e175

)

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>

* Remove CCC Upcoming Event

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Add developer meetings as upcoming events

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit d183168f

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

(cherry picked from commit bcad26c3

)

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
(cherry picked from commit ebef7f59

)

Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>

This reverts commit 5326124e.

Adds additional Scaldoc to the RegNext object that (1) indicates that
the width is not set and (2) shows an example of how to construct a
RegNext-like construct with a set width.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit b171f20d

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit f1c4395b

)

Co-authored-by: Leway Colin <colin4124@gmail.com>

* Remove redundancy code

* Remove blank line

* BitPat supports whitespace and underscores, presumably for human readability.
The BitPat.parse factory though did not remove these from the returned count.
This fixes that adds whitespace and underscores to the unit tests
This is an updated vesion of Chisel PR #1069

Co-authored-by: Chick Markley <chick@qrhino.com>
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 160e019e

)

Co-authored-by: Leway Colin <colin4124@gmail.com>

(cherry picked from commit c7715c16

)

Co-authored-by: Deborah Soung <debs@sifive.com>

(cherry picked from commit 0a98a82c

)

Co-authored-by: Adam Izraelevitz <adam.izraelevitz@sifive.com>

This is just a band aid until an Aggregate `isLit()` method (for which work has begun) is implemented.

(cherry picked from commit 98a6710c)

This reverts commit 5a0f0666.

(cherry picked from commit 03bbb258)

(cherry picked from commit 8edca94f)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit a301fa12)

Data.isLit called Data.litArg which would trigger a Chisel runtime
deprecation warning in user code with source locator Data.scala:488

(cherry picked from commit afef8b8c)

This switches from using an implicit val that required awkward
suppression (as illustrated in CompileOptionsSpec) to allowing
overriding in the same way as done in "import chisel3._" via the
creation of an implicit val in lexical scope.

(cherry picked from commit 2c53527f)

(cherry picked from commit d4f64fa6)

* Add brief description of (current) chisel versioning and version recommendations.

* Respond to comments.
Replace "semantic versioning" with "a form of semantic versioning".

* Respond to comments - replace mmddyy with yyyymmdd.

* Mention change in SNAPSHOT naming.

(cherry picked from commit 041fd377)

* Better anonymous and class-in-function desiredName

This changes the desired name of a Module to provide non-numeric
naming for anonymous Modules and Modules defined inside function
bodies.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit a69d79f2

)

* Tests for anonymous/class-in-module desiredName

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 77d2455a)

Accomplished by changing the code gen for casting literals to
aggregates. Rather than connecting the literal to a wire that is then
bit selected from, just bit select from the literal which saves the
creation of an intermediate wire and matches FIRRTL's semantics for
legal async reset initial values.

(cherry picked from commit 92d88ffb)

* Add CCC20 Info at README top

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Add Upcoming Events h2 Heading to README.md

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
(cherry picked from commit 185710d0)

Also specify 3.2.x/1.2.x branches for CircleCI

This reverts commit 7b93b0f8.

Make ChiselStage targets not private